Buck-Boost Configuration

[BadeBhaiya]

Hey guys, hope you're having a good day.

I've been really intrigued by the control software running on SMPSes so I'm making a quick-and-dirty board to play around with buck and boost topologies and hopefully write software for them (and give my new scope some action!). The board only has an STM32 micro and a few FETs with gate drivers, nothing too fancy, but I do want to support both topologies using the same inductor. I've omitted the current measurement and feedback circuitry since its not very interesting or relevant.

Does the "anti-parallel" arrangement of low side FETs look right? Maybe I should have higher voltage rated FETs in there? The input voltage is from a 48V 450W solar panel.

[Psi]

Personally i would probably drop the H Bridge driver ICs and use the MCU outputs intended for HBridge control to drive the fet gates direct. Just make sure the timer output compare on the MCU can add deadzone.

half/full-bridge driver ICs can be a bit annoying sometimes, their deadzones can be very small which can be super annoying when trying to experiment with stuff since you get shoot through and your fets tend to explode a lot unless everything is perfect. 

With the deadzone amount under software/hardware controlled you can play around with it and keep it larger to start with.

Select a MCU with the right high speed timer compare outputs intended for H-Bridge control and at a clock speed that is reasonable for doing DCDC. I think most/many STM32's have this, just check the datasheet.

When experimenting I would also recommend adding some low value resistors to each half-bridge so any shoot through current doesn't immediately pop the fets. Like 1 to 0.1 ohm or something, just to limit the current to something that will pop the fets in 5 seconds not 5milliseconds. Gives you time to notice the powersupply current is maxing out and cut the power.


You also need to use either,
N-fet on the bottom and P-fet on the top.
 OR
N-fet on both top and bottom but you need an external higher voltage (than your main voltage) to drive the top side Nfet gates to +10V.

For experimenting, i would just go with the first option, N-fet low side, P-fet high side.
The downside is P-Fets are a little more expensive and they have worse Rdson, but the circuit design is much easier than messing around with another voltage rail to drive the high side fets.


You might also want to add a large 50V clamp TVS across the thing so you can't produce 100's of volts and fry the 55V fets.
Depending on your inductor and switching its entirely possible to step up 5V to 200V.
You could use 600V fets, but even then, best to keep the voltages safe, so 55V fets and 50V clamp TVS is probably the best option for experimenting .

[BadeBhaiya]

Many thanks Psi!

Your post is truly a goldmine of information and guidance. Since the intent behind the board is indeed as an experimentation/fun, I will take your advice and replace the H-bridge driver and NFETs with a simplified PFET + NFET config. Voltage clamping and current limit resistor also sounds like reasonable precautions, along with high voltage FETs.

[Psi]

I'm no expert on this, i'm sure others will come in with more recommendations.