Need some loop stability advice (LTSpice)

[Boscoe]

Hi all,

I've never mastered analogue control loops and it bothers me. I'm trying to design this CV/CC lab PSU in LTSpice however not matter how many capacitors I've tried to place in how many configurations, I just cannot get this thing stable in CC. CV is fine.

It may well be that it's not viable with this topology and component selection.

Could anyone give me some pointers on how to tackle this sort of problem?

I understand the loop stability criteria however (in the past) I never seem to be able to improve the gain margin. I try to shift only the gain but the phase will always move with the gain so I just end up lowering loop bandwidth and not improving stability.

If anyone has any resources for developing knowledge in this area, that would be awesome too.

Many thanks!

[mawyatt]

Remember that in CV mode the starting point for stability analysis is an Open Circuit load that moves towards a Short Circuit, whereas in CC mode the starting point is a Short Circuit load moving towards and Open Circuit.

Best,

[moffy]

The simulation seems stable when I run it, but U3 provides a lot of gain for the current feedback, I am suprised it is stable.

[xavier60]

Please post the schematic.

[Boscoe]

Hi, it is attached in the OP.

[Boscoe]

The simulation seems stable when I run it, but U3 provides a lot of gain for the current feedback, I am suprised it is stable.

Yes this is very strange. I just tested again and it is stable but honestly I've been battling this thing for days! 

Do you have any recommendations on how to replace U3 or decrease the probability of oscillation? I actually want to make this however I currently have zero confidence it will work in the real world.

[jonpaul]

Suggest that you first study classique 2nd order control system théorie

Compensation is easy with a Bode plot.

between oscillation underdamped and slow response overdamped, the optimal is often critical damping.

I have never used LTspice, or other Simulators

building the circuit is easier

Bon courage


Jon

[moffy]

Yes, reduce the gain of U3, you might need to reconfigure it a bit to work properly but that is the most obvious issue.

[Zero999]

It is unstable.

[Doctorandus_P]

On a side note:

Why use the LT1210?
It seems to be a quite expensive part with limited supply voltage rails and current delivery.
It does have a quite high bandwidth though (which may add to loop stability problems)

I would be more inclined to design around an audio amplifier, maybe a TDA2050 or LM3886.

[RoGeorge]

If anyone has any resources for developing knowledge in this area, that would be awesome too.

You attached a schematic set for transient analyses, which makes me think you didn't make any AC simulations for stability.  You should break the feedback loop to see if the design met the stability criteria.

To open the feedback loop, here's an LTspice example:


A nice overview about stability from Apex:  Stability for Power Operational Amplifiers
https://www.apexanalog.com/resources/appnotes/an19u.pdf

For more verbose explanations and examples, maybe this series by Tim Green might be of help, called "Operational Amplifier Stability".  I've collected the PDFs after they were mostly gone, and now scattered all over the web.  Took a lot of searching to find them all (they were published while Burr Brown was not yet bought by Texas Instruments, and now the old links are broken).  It took so much time to find all of them that I've burned the day searching where from to download the PDFs, instead of studying them. 

There are only 11 parts (not 15), 12 to 15 were never published, according to the author.  There are some PPT continuations instead, called "Solving Op Amp Stability Issues" 1 to 4.

ToC for "Operational Amplifier Stability" by Tim Green
01.  Loop Stability Basics.pdf
02.  Op Amp Networks, SPICE Analysis.pdf
03.  Open and Closed Loop Output Resistance.pdf
04.  Loop-Stability Key Tricks and Rules-of-Thumb.pdf
05.  Real World Design of a Single Supply Buffer Circuit.pdf
06.  Capacitance-Load Stability:  RISO, High Gain & CF, Noise Gain.pdf
07.  When Does RO Become ZO.pdf
08.  Cap Load Stability: Noise Gain & CF.pdf
09.  Capacitive Load Stability:  Output Pin Compensation.pdf
10.  Capacitor Loop Stability:  Riso with Dual Feedback.pdf
11.  Modeling Complex Zo for Op Amps.pdf

The last 4 are in fact PPT presentations, easier to find, will not attach them:
12.  Solving Op Amp Stability Issues Part 1.pdf
13.  Solving Op Amp Stability Issues Part 2.pdf
14.  Solving Op Amp Stability Issues Part 3.pdf
15.  Solving Op Amp Stability Issues Part 4.pdf

[RoGeorge]

Part 8 to 10 of "Operational Amplifier Stability" by Tim Green

[RoGeorge]

And the last, part 11 of "Operational Amplifier Stability" by Tim Green

[Jay_Diddy_B]

Hi,

Try this:




I have attached the model.

I will let you figure out the changes I made 

Jay_Diddy_B

 psu_version_JDB.asc (3.46 kB - downloaded 34 times.)

[xavier60]

Instead of the Zobel network. AC feed back could be coupled from the left side of R2.

[jonpaul]

C4 1 nF very high cap load.

Add 5..100 Ohm series R

j

[moffy]

What I did was similar to Jay_Diddy_B, but U4 is also problematic as jonpaul states, and deserving of some compensation. Some opamps don't like capacitive loads, very few do, so a little compensation will help stabilise it.

P.S. This is not a final design, but merely indicative of some stabilisation methods.