Heatsink for Power SO8 package

[Ashwin619]

Hello all,

I would appreciate it if someone can identify the type of heat sink that's being used in the attached image. The component is most probably an N-channel Mosfet in one of those Power SO8 / Power DI packages. The heatsink pate is shorted to the drain of the FET, (not sure if this is intentional or not). A quick search on web shows heatsinks only for DPAK and D2PAK kind of packages.



I am planning to use one of these in my design for a buck switcher which uses similar fets. I am aware that this not the best method of using a heatsink on the plastic case rather than the pad due to bad Rth, however due to some other constraints I want to stick to the former approach.

[Konkedout]

In your image, I think I see the MOSFET but I am not sure which device you think is the heatsink?  I do not see anything that convincingly looks like a heatsink.

[inse]

The heatsink is the piece of sheet metal on top of the MOSFET.
This only works when soldered to the drain pins because those are extensions of the die attach which carries away the heat.
I can imagine that this is a nightmare to solder as you have to stack two parts before soldering and create a thermal imbalance to the opposite side during reflow.
Edit: or is the heatsink glued to the MOSFET before placing?

[Konkedout]

Ahh  OK.  I am not sure how it is applied, but it could just be a piece of custom sheet metal (tin plated copper?).  If this is a mass production pcb, the tooling charge from a sheet metal fabricator would not be a big expense relatively speaking.

[ajb]

Glueing the heatsink to the mosfet before placement would be tricky, since the bottom surfaces of both will need to be coplanar to a fairly close tolerance for reliable soldering to the board.  I would guess they’re placed separately and soldered at the same time.  It looks like there are two bends in the heatsink to form a small ‘foot’ for soldering at the board surface, if it weren’t for that the whole heatsink would be liable to get pulled vertical by the surface tension when the solder reflows.  As it is, it seems like it should solder okay.  The heatsink represents a fair bit of extra thermal mass, but heatsinks work both ways, so it may be a net benefit in getting the joint up to temperature.  I guess you would want to have a line of solder mask between the pins on the mosfet and the heatsink to prevent one from sucking too much solder away from the other, especially since the probably won’t reflow at quite the same time.

[inse]

If you look at the detail in the photo, isn‘t that probably some excess glue?
Or is it a reflection?

[Ashwin619]

Hi inse,

I think its somewhat unlikely that they have glued the metal plate to the FET before placement since this might introduce some unevenness in the surface contact of the FET to the PCB due to tolerances of the metal plate during the Reflow process. A better approach as per me would be to first solder the Fet and then stick the heatsink followed by its soldering. Some pressure on the metal plate while its being soldered would be needed. Anyways either of these processes seems to be quite a hassle during the assembly process. 

[Ashwin619]

Hi ajb,

Glueing the heatsink to the mosfet before placement would be tricky, since the bottom surfaces of both will need to be coplanar to a fairly close tolerance for reliable soldering to the board.

This makes sense.

It looks like there are two bends in the heatsink to form a small ‘foot’ for soldering at the board surface, if it weren’t for that the whole heatsink would be liable to get pulled vertical by the surface tension when the solder reflows. As it is, it seems like it should solder okay.

You are correct. There are 2 bends with one of the smaller flat surface making a direct contact to the drain pad on the PCB.

I have forgotten to mention that this board also uses an RF shielding can as a kind of a heatsink. The can makes contact with the metal plate on the FET via some thick spongy thermal pad kind of material. Will try to post the image once I find it back.

Thanks for your inputs !!!

[Ashwin619]

Hello all,

Here's a glimpse of the layout that I am working on -->





The idea is to have some thermal vias on the drain pad and small copper plane on the other side of the PCB. Need to estimate the power losses on the FET's and to take a call whether heatsink is even needed or not.
The switcher is supposed to provide 5A continuous at 7.4V with no option for air convection due to the enclosure.
I have left some mounting pads for the RF shield in case if it can be used as a heatsink.
Meanwhile also looking for some other options of using a heatsink on the exposed drain pad on the other side of PCB. Any suggestion here would be appreciated.

Regards,
Ashwin619.

[electron_plumber]

It’s easier to punch thermal vias through the PCBA and thermally interface with a heat sink on the opposite side of the board.

But I’d calculate the thermal impedance necessary for junction temperature margin given your loss estimates before you add an assembly step.

[PCB.Wiz]

The switcher is supposed to provide 5A continuous at 7.4V with no option for air convection due to the enclosure.

That’s not massive, so you may be better to put a few cents into thicker copper on the board, and a lower rds fet, to avoid the extra messing about.

[Ashwin619]

It’s easier to punch thermal vias through the PCBA and thermally interface with a heat sink on the opposite side of the board.

Yes, that's the plan. I have placed some thermal vias on the drain pad of the Fets and will be interfacing it with the heatsink from the other end.

I have done some preliminary calculation for the FET losses and required Rth comes out to be at around 23.1 °C/W. The power loss (mostly the Switching losses) for the HS Fet seems to be quite significant at around 5W. This is probably due to the slow rise and fall times arising because of gate resistor, which is at 4.7ohms at the moment. Ill try to reduce to optimize it better.
Currently I don't have any means of doing some kind of thermal simulation for the above required Rth. Will check the thermals once the first revision is made.
Some additional design specs that i forgot mentioning before.
Fsw = 300kHz
Vin max = 35V
Iout max = 5A





Let me know if I have missed something over here...

[Ashwin619]

That’s not massive, so you may be better to put a few cents into thicker copper on the board, and a lower rds fet, to avoid the extra messing about.

Yeah, its probably not much but I still need to ensure that the Tj remains in limits especially considering that there's no way to extract the heat out other than the PCB copper and the heatsink. I might plan for 2 oz of copper or more for better dissipation.

I am using these these FET's for both HS and LS,
https://www.lcsc.com/datasheet/lcsc_datasheet_2003241812_Infineon-Technologies-BSC0702LS_C501503.pdf

which has around 2.7m Ohm max Rdson. The major contributing factor to the power loss is not conduction but rather the switching one which I am planning to further reduce by optimizing the gate resistor.

[Kurets]

I would actually think that 2.3mOhm sounds like too low rds on for efficient switching. These are low voltage FETs I suppose, which I am not used to working with, but I would think that increasing on-resistance by a factor of 10 would not be a problem, and it would allow you to use a device with lower Qg, lowering switching losses.

Dissipation in the device would still push you towards faster slew rates for lower device dissipation, but it may end up being more optimal in the end.

[electron_plumber]

In my experience, 15-20C/W is achievable with an SO8 FET thermal via'd to a low-side heat sink. However, your calculations are assuming 25C? In reality, your PCB will heat up around the FET.

You can solve this, thermally, but I'd recommend revisiting your design calculations to see if you can reduce the 5W of continuous dissipation. How much load current are you designing for? You're using the same FET for low- and high-side switching -- what is your duty cycle? You might be able to squeeze out more performance by optimizing the low-side FET for conduction rather than switching losses. Keep in mind the reverse recovery losses from the LS FET ultimately get dissipated across the high-side switch.

Edit:

I just saw this comment: "The switcher is supposed to provide 5A continuous at 7.4V with no option for air convection due to the enclosure."

Notionally, you shouldn't be dissipating 5W across either FET with only 5A load. What are your input voltage, switching frequency, and gate driver/controller?

Anecdotally, I've pushed single-phase bucks to nearly 20A continuous with S08 FETs and only passive heating. You should have no trouble with a 5A load if designed properly.

[Ashwin619]

but I would think that increasing on-resistance by a factor of 10 would not be a problem, and it would allow you to use a device with lower Qg, lowering switching losses.

I believe its the usual trade off between low Rdson and low Qg which I need to optimize further. The current FETs have a Qgs and Qgd of around 10nC typ and 11nC max respectively. The calculation shown in the datasheet of the MIC2127 switcher ic considers the effective Qg to be around (Qgs/2 + Qgd), which seems like an approximation. I need to verify whether this is the correct way or not.

[Ashwin619]

Notionally, you shouldn't be dissipating 5W across either FET with only 5A load. What are your input voltage, switching frequency, and gate driver/controller?

Yes, I agree with you regarding the switching losses, which is quite high at the moment. Here's some of the specs of the board -->
Vin = 6 - 35V
Fsw = 300kHz
Buck switcher ic = MIC2127A

This design is referenced from an another project and not designed by me, I am just trying to optimize it further.
I am able to reduce the total dissipation from 5W --> 3.3W by reducing the gate resistance from 4.7ohm --> 1ohm. This is excluding the additional series resistance from driver and the FET.
Note that the total dissipation of the HS FET is 5W, which includes Conduction, Switching, Diode Reverse recovery and Coss losses. The switching one accounts for 80% of that.
 
I always used to believe that the usage of different FET for HS and LS had more to do with the false triggering of the LS FET due to high dI/dt of the switching node caused by Cgd. The conduction losses seems to be quite low at around 50-79 mW due to the low Rds on. I remember there was an application note on how to select the HS and LS FET's for the Synchronous Buck switcher. Maybe Ill find and refer it again to select the proper FET's.

Thanks for you suggestion.

[electron_plumber]

I am able to reduce the total dissipation from 5W --> 3.3W by reducing the gate resistance from 4.7ohm --> 1ohm. This is excluding the additional series resistance from driver and the FET.

Ah, that's a nice clue that you're dissipating lots of switching energy. The gate driver you're using has 2-4 ohms of pull up/down resistance. You can probably get away with reducing those gate resistances to 1ohm with proper gate loop layout, with a caveat that you'll want to closely examine switching transients during validation.

I would try recalculating your loss stack with some lower Qoss FETs. As an example:

• high side: https://www.onsemi.com/download/data-sheet/pdf/ntmfs6h836nl-d.pdf
• low side: https://www.onsemi.com/pdf/datasheet/nvmfd6h852nl-d.pdf

I always used to believe that the usage of different FET for HS and LS had more to do with the false triggering of the LS FET due to high dI/dt of the switching node caused by Cgd.

Just make sure the capacitive divider (formed by Cgs and Cds of your LS FET) doesn't inject enough gate charge to turn/enhance the LS FET at all when the switch node swings high. This capacitive divider approximation is a simplification, as these capacitor terms are actually nonlinear functions of applied voltage (see paper 1 below), but this mental model gives the right intuition (see ls_fet_cap_divider.png attachment for a quick illustration).

The conduction losses seems to be quite low at around 50-79 mW due to the low Rds on. I remember there was an application note on how to select the HS and LS FET's for the Synchronous Buck switcher. Maybe Ill find and refer it again to select the proper FET's.

Here are a few papers I would recommend -- the first one from vishay in particular is really good:

• https://www.vishay.com/docs/73217/an608a.pdf
• https://www.ti.com/lit/an/slpa009a/slpa009a.pdf
• https://www.ti.com/lit/an/slyt664/slyt664.pdf