Help choosing a schottky diode

[criossantking]

I have drawn up schematics for a USB interface on a PCB that was not populated from factory (it was used for prototyping purposes, most likely).

The specifications for the CMD 0670 chip (http://www.bitsavers.org/components/cmd/MAN-000670-000_USB0670_673_PCI-USB_ASIC_Rev_1.8_199903.pdf, section 7.1.4) call for a Schottky diode clamp at location D2, to prevent VDD3 (+3.3V) from exceeding VDD (+5V). It says:

The USB670 has two power rails: VDD at 5.0 volts, and VDD3 at 3.3 volts. It is IMPERATIVE that the VDD3 never exceeds VDD: otherwise a latchup may occur, destroying the chip. During power-up, VDD and VDD3 may rise at the same time, provided VDD3 does not exceed VDD. In practice, limiting VDD3 to less than 0.3V more than VDD is generally acceptable if the injection current is small and of short duration. Upon power-down, it is acceptable to have VDD collapse before VDD3, provided the current through any power supply pin is limited to less than 50 mA for no more than 5 milliseconds worst case. A Schottky diode clamp may be used to ensure this if it is not otherwise part of the system design. Undershoot upon power-down should also be limited to less than 0.3V (reversed polarity) on any power supply pin. This can also cause latchup.

Here is the relevant part of my schematics:


Physical location on the board:


Full schematics also attached.

I just wanted to confirm I've got the orientation correct (anode to VDD3, cathode to VDD) – my understanding is that if VDD3 goes above VDD then any excess voltage will drain through the diode, protecting against a latchup. I also wanted to confirm a SS14 diode would be suitable here. I used some calipers to check the footprint and the DO-214AC package seems appropriate.

[ArdWar]

Where VDD3 are generated from?
With such strict requirement it might be better to derive VDD3 locally from VDD5 using LDO that guarantee power sequencing instead.

Otherwise empirically speaking almost any Schottky should work fine. Assuming that the internal ASIC structures are all silicon and the posted 0.3V limit is a rather cautious safety margin.
But it's technically very easy to (slightly) exceed the 0.3V maximum instantaneous voltage during power down especially with the various bulk caps in VDD5.

[criossantking]

Thanks for sharing your ideas and concerns.

The PCB is already mass produced so I can only really work with the footprint that's already there. I have been using my design for a while with D2 unpopulated, and I haven't seen any problems. But I would like to add it in.

Do I have the diode the right way round in my schematic?

[criossantking]

Nobody can help advise regarding polarity?

[criossantking]

Just giving my post a little bump. Would much appreciate some help. Thank you in advance

[youngda9]

Your polarity is correct.  Lots of options with that package, check out Digi-Key.  CDBA140SL-HF might be a good option.

[criossantking]

Thanks for confirming this - very much appreciated.

What were your criteria for suggesting this diode?

[youngda9]

I just went searching for Shottky diodes.  Narrowed it down to in stock, available, and in the package that you need.  I then sorted by lowest voltage and looked at that one, which seemed reasonable.  Not sure what other criteria that you may have.

[Njk]

It's hard to suggest other criteria without the idea for where's the power voltages are sourced from. E.g. consider the case when Vdd3 is on while Vdd is off. If that can happen (for instance, during debugging) then the diode shall be rated for all Vdd current (at the Vdd3 voltage)

[youngda9]

Then you can add that into the search criteria.