Dual port DSI panel only half accessible

[david_geng]

Hi,

I'm trying to use a sharp LCD panel with R63419 control via the command mode only to save some interfacing cost as the picture update rate is very low.

So far I think I can configure those registers and turn on the display. However, when I wrote the pixel data to the R63419 framebuffer RAM, only half of the RAM was actually accessible. So far the test and results are,

1. build-in test runs ok and show the full display;
2. set_all_pixel_on show all pixel on;
3. control of the TE output signal ok.

So by the 3 tests above, can I assume the register setting and the memory mapping/scanning are ok?

The forth test did annoy me a lot,

4. after setting 0x2a and 0x2b (col and row address), I tried to write the framebuffer RAM through LP command mode, i.e. by the 0x2c and 0x3c long packet command. Data could be written, but only showed on half of the panel.
4a. since I was writing the whole frame data, I could see the data been overlap twice during the writing procedure, i.e. twice on half of the panel. but I've set the 0x2a to 0x00 0x00 0x05 0x9f which is the full width.
4b. if I change the 0x2a, for example, to 0x03 0x00 0x05 0x9f trying to force writing the other half, I could only see a vertical line in the middle.
4c. since this is a dual link DSI panel, I tried to use N0B and P0B instead of N0A and P0A, nothing showed up.

So my question is, would it be possible to access the full RAM via LP command mode? did I miss any register setting? If the LP mode has some limitation or bug, would HS command mode give the full access to the RAM?

Any thoughts or experiences would be most appreciated.

regards
David

PS the pixel is uncompressed 24bit data, and I did try to write a block of two lines at a time according to requirement of the datasheet, but not making any difference.

[bktemp]

That behaviour sounds familiar.
On some dual channel MIPI-DSI displays the lanes are hardwired to the left and right half of the screen. So the first 4 lanes can only drive the left half of the sceen and the second 4 lanes the right half.
LP mode is implemented only on the first lane of the first channel, so it is probably impossible to drive the full screen via LP mode.