Devices with PWM that cannot be fully disabled will not meet my requirements. Most of these produce a brief pulse when the counter reloads, with a maximum pulse width typically around 99.98. This results in an unwanted pulse, and, given that the clock in most of these devices is internal, there is no way to control when that pulse occurs.
At this point, I’ve lost track of the specific devices that specify settling time, though I believe one might have been from ROHM or a similar manufacturer. After reviewing approximately 150 datasheets, I’ve even considered single-channel devices.
Currently, I’m inclined to use a simpler LED driver functioning as a shift register with fault detection, provided I can find one that meets my timing requirements. My plan involves placing a current sense resistor in series with the output and using three 16-channel ADCs for fault detection. Fault detection would be performed only at startup, shutdown, and after each test—primarily to check for output failures and confirm device contact with the test jig. Consequently, fault scanning times are not critical.
There is additional complexity in the overall circuit that I haven’t detailed here. However, the other sections can be isolated similarly, and I am focused solely on this isolated portion for now. While other voltages and currents will be applied to the outputs, this solution will be isolated during those test phases. A full explanation would require more detail.