Also there is no mention of INL + DNL or ENOB BUT there is a table at the end regarding RAIN(
) which I'm not sure what input resistance that is exactly. Maybe you can make sense of that and how accurate it is?
The Parameters are in the sheet, but it looks like ST made own shorts
EL = INL = 11LSB
ENOB = 12.2 bits
Total Unadjusted error = +10 -20 LSB
16 bit resolution sounds plenty. With so much resolution there is no need to switch the gain, at least not in fine steps. Digital pots tend to be relatively slow with quite some unwanted internal capacitance. In addition the fet switches can act nonlinear. I would consider adjusting the high voltage to trim the gain if needed.
Yes this is kinda true, but 16-bit ADC usually do not really have 16-bit Resolution because of error
AFAIK the energy resolution is often quite limited, so more like 10 or 12 Bit. This is especially true for the more low cost type detector.
This is true, usually there are 4k or 8k channels, so you need at aleast 13 valid bits to fill 8k Channels
For the OP I would expect something like a relatively fast CMOS OP, maybe LTC6240 or similar of price is not that important. The baseline (DC level) can probably be subtracted in software.
I have this one in stock. Maybe i will try it
An important factor would be the expected count rate. The more the less pulse stretching is possibly without loosing to much to pulse collision.
Usually big detectors put out 50 counts per second in a normal room and in my experience i never got more than 2000 cps. Since the Si-Detector is much smaller, i except around 1000cps as a maximum count rate.
If OP provides more details, then perhaps we can make better recommendations.
Also MCUs usually advertise their ADCs as X number of bits but in reality they perform way worse.For example the popular ATMEGA-328P advertises 10 bit ADC but INL and DNL are about 2LSB, so really it's only an 8 bit ADC with a bunch of added noise. That's why I mentioned the noise figures don't seem to exist on the ST datasheet, at least not in a way that makes much sense to me.
Are you sure 2LSB is referenced to resolution bits? As far as i know, LSB are stated as the difference in value, not bit position 2LSB would mean that a binary value at 10 bit would have differences in the last 2 bits, not completely remove them. For example:
1111 1111 00 could be either 1111 1100 11 or 1111 1110 00, not remove 2 bits and reduce the resolution to 0 - 111 111 ?
More details:
The Goal is to first shape the Output to a better geometrical property. With the current shape, it will be very hard to have correct sampling, because the peak of the signal is almost immediately after the trigger threshold. If the curve rises smaller, there is more time for the MCU and ADC to get the values. Also the current signal is to short to be sampled with 2MSPS or 3.6MSPS and get the peak.
The gain of the amplifier does not have to be dynamically switchable, more like 2 or three gain settings. For example, when operating on low pulse height (low bias), lets say 0-500mV, it would be a shape to waste the remaining 2000mV (2.5V ref) of resolution because of fixed gain. If the signal is amplified by 4 in this case, you have 0-2000mV of Resolution. In high pulse height mode (high bias), there would be a gain of 0 needed, because the pulses already reach 2.4V of height. Also, lowering the bias voltage to control the gain, is no option, since it must support different bias voltage, because bias voltage changes behavior of the detector.
Lets say i would need at maximum 3 Settings of Gain (0, 2, 4) and could live with 2 settings (0,2). They do not have to be fast or dynamically switchable. The idea with the analog switch I've seen in a commercial detector fronted by Amptek, but made for different detector. See image for the Circuit. But i do not need 4 gains. I will look into the digital pot solution that was proposed
The Signal is random each time, by the pulse-height of the signals a spectrum can be drawn where its possible to see peaks in certain values, looking roughly similar to those EMC test-reports (just as a reference how it will look). The gain will be set and fixed for the measurement and will be calculated from the bias. For example bias 25-27V will be Gain 2, and 28-32V will be Gain 0.
As stated, usually there are 4096 or 8192 Channels available, but they have to be valid. The idea is to round pulses into a certain value. For example, an equivalent of a value of 1023.4 would be binned as 1023, and 1023.6 would be 1024. BUT! The initial accuracy must be at least as good as the channels. For example, if you have 4096 channels, the ADC resolution must be at least 12bits.
Lets say we take a "perfect" 16-bit ADC with 0 Error as example. It would output values between 0-65535. With 4k Channels, on a 16bit ADC there would be a channel each 16 Values
For example:
Channel - ADC Val
0 0
1 16
2 32
...
1000 16000
1001 16016
1002 16032
1003 16048
1000 is binary 0000 1111 1010 0000
1001 is binary 0000 0011 1110 1001
1002 is binary 0011 1110 1010 0000
1003 is binary 0011 1110 1011 0000
So to in case of this case, we can say the last 3 binary values can be ignored, or just be binned to the next channel value.