Help with part of a schematic

[mayor]

Hello,

in this circuit: https://www.waveshare.com/w/upload/8/87/E-Paper-Driver-HAT-Schematic.pdf

I am wondering why not drive the gate of the mosfet directly (threshold voltage is manageable)?

[inse]

Depends on the supply of the driving circuit, if it is not supplied, the MOSFET could be turned on by the current through the protection diodes of the IC or uC.
Decoupling via a transistor solves this issue.

[mayor]

Depends on the supply of the driving circuit, if it is not supplied, the MOSFET could be turned on by the current through the protection diodes of the IC or uC.
Decoupling via a transistor solves this issue.

So to clarify, if the gate is actively driven with a GPIO? Wouldn't that be fine?

[moffy]

There is a bit of logic going on between the VCC_EN and EPD_RST as well as just enabling the supply.

[mayor]

There is a bit of logic going on between the VCC_EN and EPD_RST as well as just enabling the supply.

Yeah but even then, the transistor isn't necessary for that bit, right?

[antenna]

i didnt look at the datasheet, but here is a simple reason I would have that transistor there... Most mosfets are not fully "on" at 4 or 5v whatever Vgs..  To make sure it is all the way on and off at max current capability, its best to drive the gate as close to the rail voltages as you can.  If you don't, there could be some extra Rds you dont want and it will get hot.

[moffy]

There is a bit of logic going on between the VCC_EN and EPD_RST as well as just enabling the supply.

Yeah but even then, the transistor isn't necessary for that bit, right?

But the transistor makes life easier and better, for the other reasons mentioned as well.

[SiliconWizard]

Another factor: this is a board intended for a RPi. Its GPIOs are 3.3V, but the PMOS switches VCC_INT which is 5V here if I'm not mistaken.

Meaning that if the gate was directly connected to a GPIO, it may not be able to switch off the PMOS properly. There is a pull up to VCC_INT, but it will do nothing when the RPi is actively controlling the GPIO. It will keep the PMOS switched off when the GPIO is in high impedance though.

The fact that you'd find 5V on the GPIO through a 47k resistor would be harmless per se for the GPIO itself when it's in high impedance.

I don't know enough about the RPi GPIOs, and the library/language used here, to know if you can properly put them in high impedance programmatically. If so, a program could just set the GPIO to output/low level to switch the PMOS on, and set it to high impedance to switch the PMOS off, instead of setting it to a high level (which again would probably not work well.)

[Daniel Perez LW1ECP]

I began writing this:
I see Q31's source terminal is connected to 5V from RPI, and U1 is fed with 5V. As U1's EPD RST swings between 0V and 5V, then it's ok to drive the MOS without Q32 and resistors. But you need to change something in software to reverse states, because Q32 is an inverting stage.

BUT I was wrong! I was missing the VCC ENable line: it feeds the EPD RST to U2 to enable the regulator, so you can't invert state in software, or else U2 will work the opposite.
In a nutshell: leave the schematic as is.

[mayor]

Meaning that if the gate was directly connected to a GPIO, it may not be able to switch off the PMOS properly. There is a pull up to VCC_INT, but it will do nothing when the RPi is actively controlling the GPIO. It will keep the PMOS switched off when the GPIO is in high impedance though.

Ah yes! Thank you! I was abstracting that fact away as I intend to use 3.3 V throughout in a reworked circuit.

BUT I was wrong! I was missing the VCC ENable line: it feeds the EPD RST to U2 to enable the regulator, so you can't invert state in software, or else U2 will work the opposite.
In a nutshell: leave the schematic as is.

Yes, true, and it's necessary here. I wasn't clear on my intentions, as I can do away with that part.

Thanks all.

[mayor]

So, coming back to a different part of the circuit...



I'm now trying to understand the RST part. The RPI controls EPD_RST' (3V3), which sets EPD_RST (5V) through the level shifter.

I get confused because RST is used to enable 3V3_OUT, which the level shifter depends on for Output Enable, so it's really not clear how changing RST' can even change RST if its initial state is low.

Your help appreciated once more :-)

[inse]

And the Vcc supply of the level shifter is also controlled by himself...

[mayor]

And the Vcc supply of the level shifter is also controlled by himself...

Yes, hence the confusion! I thought there might be a mistake and that the gate of the transistor might actually be controlled by RST', but no, I traced the working board, and it's according to this schematic.

[inse]

Is this the product?
https://www.waveshare.com/product/raspberry-pi/e-paper-driver-hat.htm?___SID=U

[mayor]

Is this the product?
https://www.waveshare.com/product/raspberry-pi/e-paper-driver-hat.htm?___SID=U

Yes!

[mikerj]

And the Vcc supply of the level shifter is also controlled by himself...

Looks like a great recipe for appearing work until it doesn't.

[inse]

I keep thinking about this comment