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Help with STM32duino timers and frequency measurement

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profdc9:
I attempted to publish in QST/QEX but they rejected.  Also in another UK amateur radio society journal.

There is a 60 page document in the project explaining how it works.

https://github.com/profdc9/ModularTuner/blob/master/doc/ModularTuner-Guide.pdf

timdf911:
Surprised it was rejected as they are usually begging for contributions.  I have subscriptions to both QEX and RadCom.

I've had several articles published in RadCom over the years most recently in January 2023 and this problem of measuring frequency is part of a follow up article.

I'm licensed as KT6UK / G4WIM

Making good headway with the design now I've found an adequate frequency measuring solution.

Edit - just been reading your document and what a great piece of work which has many parallels to what I'm working on.

Regards Tim

ozcar:

--- Quote from: timdf911 on December 15, 2022, 08:32:42 pm ---Hi ozcar

the 4MHz limit was because I had the system clock set to about 8MHz rather than 84MHz.  Yes because the frequency counter is only 16 bits I have to make sure the max count is within limits so I have the ETR2 prescaler set to /8 and use a 8mS gate as this gives more stable results compared to no ETR2 prescaler and a 1mS gate.

The counter easily goes to over 55MHz with 1kHz resolution.

As mentioned above due to HW constraints I'm forced to us PD2 input pin which connects to 16 bit timer.

Certainly has been a good learning exercise and worth the effort and time - I appreciate your help.

Regards Tim

--- End quote ---

Definitely something not right there in regard to the 55MHz max. I tried with 8.4MHz timer clock, and ETPS set to divide by 8, so expected max frequency of (8.4/2)*8 = 33.6MHz. I found that it worked for input frequency 33MHz, but failed for 34MHz.

It somehow hurts to think that you have two 32-bit timers, but can't make use of either of them. You don't seem to be short of pins if you can afford to use two of them, PA5 and PB0, to tie two timers together, so what is it exactly that forces you to used PD2 as the input?

And why the 8MHz system clock?

timdf911:
yes it's very sad that I'm confined to use a 16 bit counter but none the less it provides adequate performance for my needs.

As for using some other counter / pin which is 32 bit, sadly as this part of the design is an after thought all the other counter pins have other stuff attached to them for control / sensing of ancilliary hardware.

If I had a clean sheet of paper I would have mapped things differently - but as it stands I've effectively painted myself into a corner and thus PD2 is the only option.

Just to clarify when I accidentally set the system clock to 8MHz I was not using the /8 ETPS thus 4MHz maximum.

Regards Tim

ozcar:
Quite likely I am flogging a horse that you have already interred, but my excuse is that I want to learn more about the STM32 timers myself.

--- Quote from: timdf911 on December 17, 2022, 07:32:10 pm ---yes it's very sad that I'm confined to use a 16 bit counter but none the less it provides adequate performance for my needs.

As for using some other counter / pin which is 32 bit, sadly as this part of the design is an after thought all the other counter pins have other stuff attached to them for control / sensing of ancilliary hardware...

--- End quote ---

However, prior to this afterthought, you were evidently not using PA5 and PB0, because according to this, you have now tied them together:

--- Quote from: timdf911 on December 14, 2022, 12:53:40 pm --- ... the time base signal pops out from TIM2 on PA5 then is hard wired back into PB0 to gate the counter on TIM3.

--- End quote ---

Now, it just so happens that one of the alternate functions for PA5, is the 32-bit TIM2 ETR input. That would require using some other pair of available pins to tie together, but did you really go through all the spare pins you have without finding a way to get an input capture trigger to a TIM2 channel? Even if there really is no pair of pins that allow that, the gated slave mode, which does not require any external cross link, is still possible.