Author Topic: Here's my schematic to prevent over-charging a capacitor, help please.  (Read 837 times)

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Offline bsodmike

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Hi all,

This is a simple circuit that I've setup on breadboard that I plan to later use on a Supercap.  The goal is simple - to maintain a maximum voltage and prevent the capacitor to charge beyond said cutoff voltage.

I've got a 10vdc voltage reference and an OpAmp working as a simple comparator.  The OpAmp output drives V(gs) (which has a max of 20vdc) for the MOSFET I'm using.  The issue I'm facing is that when power to the circuit is turned off, the capacitor voltage drops to 8.4VDC from the 10vdc maximum.  Tried adding a 1kOhm to tie the MOSFET gate to ground, to ensure it turns off, but that did not have any effect.

Adding a bypass capacitor across the supply rail V(sup) caused the capacitor to drop to ~6v.

I haven't had much time to troubleshoot this at the bench but if you can spot the culprit, give me a shout please!



Cheers :)
 

Offline bsodmike

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Quick update: I also isolated the 10v voltage reference during circuit power-off, by providing the 10v reference from my bench supply.

Still not entirely sure where 1.6V is being lost. Tried removing the LED on the breadboard as well just to double check.  Hmm, I'm also assuming the OpAmp inputs are high-impedance during power-off and this may not be true!  :-//
« Last Edit: April 13, 2021, 10:00:07 am by bsodmike »
 

Offline bsodmike

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https://e2e.ti.com/support/amplifiers/f/amplifiers-forum/733153/opa211-input-protection-when-power-supply-is-turned-off

I'm going to try adding a resistor at the non-inverting input to see if I can limit the voltage drop, this will definitely give me a clue.
 

Offline coromonadalix

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I dont understand youre whole idea,  a supercap is not a battery,  everything connected to ot will make it drop ??

And you want to design an overcharge protector of somekind ??  if its a 5 v supercap, supplying 5v max will never damage it or overcharge it ??

Even adding a variable or programmable cut off voltage,  what is the end purpose ?

A voltage reference ??             

A supercap will act as a battery for any mcu time clock related,  but its not infinite ?? you have internal leakage, internal resistance,   even charging it and put it on a desk, it will empty itself
« Last Edit: April 13, 2021, 10:48:12 am by coromonadalix »
 

Offline ZeTeX

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It seems like you're trying to simple charge a super capacitor?  This circuit should work:


 

Online NiHaoMike

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It seems like you're trying to simple charge a super capacitor?  This circuit should work:

Put the current limiting resistor on the input, that way the current will only drop a small amount until the voltage limit is reached instead of slowing way down as the capacitor charges up. Or use a modern LDO that has adjustable current limiting and reverse current blocking built in.
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Offline bsodmike

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Hi all,

Please watch this video -


I decided to take a different approach and use an OpAmp and MOSFET instead of the configuration those PCBs come on.

Sure, the voltage regulator approach is the easy way, I wanted to learn a bit more about this more discrete component approach.

Did a fair bit of troubleshooting and it looks like if the MOSFET gate drive pin is pulled to ground via 1M\$\Omega\$, its a lot more stable, but I need to confirm it this weekend.
 

Offline gnuarm

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I'm not clear on what is powered up and what is powered down in this design, but yes, your op amp will draw power through the inputs. 

That's not the main issue with your design though.  The main issue is that you constructed it as a shunt regulator rather than a series regulator.  A shunt regulator draws current to bypass the cap which is wasteful and not useful.  So why do that?  Instead put the FET in series with the cap, in place of the resistor from the diode.  The diode is still useful, so keep that... but, to prevent current flow into your op amp when it is powered down, swap the diode and FET so the diode is closer to the cap and the FET connects to the input power.   Now connect another diode between the tie point of the first diode and the FET with the cathode to the inverting input of the op amp.  A 10K resistor should go to ground from the inverting input.  The diode drops will be about the same, so the op amp inverting input will be about the same voltage as the cap, but no current will flow into the op amp input when powered off. 

The voltage reference will be connected to the non-inverting input of the op amp.  The resistor on the gate does pretty much nothing since the op amp will be driving it or pulling it to ground. 

I didn't look at the video, but it seems to be using bipolar transistors which are fine for this.  But you should consider limiting the inrush current.  The op amp circuit dumps as much current as possible into the cap.  Perhaps an RC from the voltage reference to provide a very slow ramp to the cap.  Or better yet a constant current source. 

I once designed a constant current source to charge a supercap using a bipolar transistor BE junction to set the voltage drop across the current sense resistor.  I don't think it charged to a voltage below the input power.  Rather it charged at constant current to the point it could not maintain that current (some 90% or so of the input voltage) then RC charged the rest of the way up as the FET was turned on 100%.  To limit the max voltage a comparator could be used to limit the voltage by taking away the FET gate drive on reaching the needed voltage.  If you want I will dig up the schematic.  It is in LTspice so you can simulate it if you like.
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Offline bson

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Still not entirely sure where 1.6V is being lost. Tried removing the LED on the breadboard as well just to double check.  Hmm, I'm also assuming the OpAmp inputs are high-impedance during power-off and this may not be true!  :-//
The signal pins are probably connected to the supply pins with TVS diodes.  Anything on a pin, especially the output, may power the op amp, except it will be out of spec (inputs too close to rail) and in some latched-up metastate or something.
 

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Offline bsodmike

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Re: Here's my schematic to prevent over-charging a capacitor, help please.
« Reply #10 on: April 14, 2021, 08:36:28 am »
With regards to the issue I was facing with the shunt regulator, and on powering down the circuit noticing ~1.6vdc being dumped from the cap - I tried tying a NPN transistor between the Cap anode and FET Drain; this helped vole this but is a really crappy solution.  On power-down the cap would drop from 10 to ~9.1Vdc.; Your suggestion is far better as you've accounted for the wasted power loss in the shunt regulator configuration.

That's not the main issue with your design though.  The main issue is that you constructed it as a shunt regulator rather than a series regulator.

Ha, good point!  Please see attached schematic as per your proposed changes.  Do we need R(lim) at the Drain of the FET? I just feel that we should limit the maximum charge voltage to the cap.

Let me know if I need to fix anything further in the revised schematic - thanks!

I didn't look at the video, but it seems to be using bipolar transistors which are fine for this.  But you should consider limiting the inrush current.  The op amp circuit dumps as much current as possible into the cap.  Perhaps an RC from the voltage reference to provide a very slow ramp to the cap.  Or better yet a constant current source.

Another great idea - yes, I noticed the instant turn on was pretty hard and an RC might work just fine; I'll do some testing later.

I once designed a constant current source to charge a supercap using a bipolar transistor BE junction to set the voltage drop across the current sense resistor.  I don't think it charged to a voltage below the input power.  Rather it charged at constant current to the point it could not maintain that current (some 90% or so of the input voltage) then RC charged the rest of the way up as the FET was turned on 100%.  To limit the max voltage a comparator could be used to limit the voltage by taking away the FET gate drive on reaching the needed voltage.  If you want I will dig up the schematic.  It is in LTspice so you can simulate it if you like.

If you don't mind sharing it, I'd like to take a look thanks!
« Last Edit: April 14, 2021, 01:20:29 pm by bsodmike »
 

Offline bsodmike

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Re: Here's my schematic to prevent over-charging a capacitor, help please.
« Reply #11 on: April 14, 2021, 02:54:40 pm »
@gnuarm - using your modified circuit I've just toyed with the LTspice sim (attached).

The pink trace is the current through the cap; in green the cap voltage measured at its anode.  Looking good!

Thanks.
 

Offline gnuarm

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Re: Here's my schematic to prevent over-charging a capacitor, help please.
« Reply #12 on: April 14, 2021, 05:12:23 pm »
This circuit uses two transistors to do what the op amp and transistor are doing.  The BE voltage of the PNP serves as the voltage reference for the current setting.  This makes it temperature sensitive, but the addition of the Schottky diode helps to mitigate that in addition to preventing back current flow when the power source is off. 

Be aware this circuit does not limit the voltage to the cap being charged.  In this app I wanted to charge as close to the incoming voltage as possible. 

Simple charging schematic
[attachimg=1]

Simple charging plot
[attachimg=2]

The gate drive to the main current handling FET Q1 is the voltage on R3.  Current limiting is controlled by Q2 which pulls up on R3 as the current through R1 increases reducing gate drive and providing regulation of the C1 charging current.  R3 in conjunction with the voltages across D1 and Q2 BE junction set this current.  Ignore the comments on voltages, that is from a previous iteration and was not updated.

C2 with R3 set the start up ramp if you don't want the current to ramp up too fast (important in many semiconductor applications).  R2 is the bleed resistor for C2. 

Here is the same basic circuit with Q3 and Q4 added to give a voltage limit.

Voltage limited charging schematic
[attachimg=3]

Voltage limited charging schematic
[attachimg=4]

Q3 acts like Q2 to remove the gate drive from Q1, but under control of Q4.  D2 and Q4 BE junction act as the differential inputs on an op amp to pass current on Kill as the C1 voltage approaches Vref.  As Kill is pulled down Q3 pulls up on R3 removing gate drive from Q1 limiting the voltage on C1.  Vc1 reaches 10.04V as the simulation ends.  The reverse current flow when power drops is in the nA range. 

I like this addition.  Nothing wrong with using op amps or comparators.  They can give very precise control over the various settings.  But I like a nice, clean transistor design as well.  It is much simpler to make sure you are not violating any specs.  Speaking of violating specs, the Vbe on Q4 will go to -Vref when power is off which is more than most transistors are rated for.  So be sure Vref is off as soon as power fails.  Seems even if the power level is not high, reverse current on the BE junction alters the transistor characteristics... or so I've been told.  Maybe a  reverse diode across Q1BE is in order. 
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Offline bsodmike

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Re: Here's my schematic to prevent over-charging a capacitor, help please.
« Reply #13 on: April 15, 2021, 06:28:04 am »
@gnuarm - thanks for the transistor based design, really useful info!

With regards to the spice schematic I shared with you (based on all the changes you recommended), how would I incorporate a constant current source to limit inrush current?

In the past I've used low-side sensing, which means adding say a 1R shunt resistor (or current-sense resistor, same thing) between the capacitor cathode and ground.  This lets us measure the voltage drop with reference to ground, and is generally handy (otherwise we'd need a comparator etc. if we were doing high-side sensing).

Of course, this means that we would be measuring the voltage across the resistor and passing that as feedback to the Opamp - a typical constant current control loop.

However, I'm not sure how this would limit in-rush current?  As for an RC circuit, yes this could work.

Thanks!
 

Offline gnuarm

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Re: Here's my schematic to prevent over-charging a capacitor, help please.
« Reply #14 on: April 15, 2021, 07:07:10 am »
Inrush is probably a poor choice of term for the issue this design will have.  Or maybe it is exactly the right term.  My point is you are charging a cap, so by definition if you apply a voltage source it will have an arbitrarily high current at first and must be limited.  Your resistor does that.  But it charges at ever lower rates as the capacitor voltage rises.

I saw a design here not too long ago that used an op amp for each part of a current/voltage regulated power supply, which is what you need.  It used separate op amps to sense the current and voltage on the output and combined them with diodes in a way that allowed either to limit the output.  That is essentially what my circuit does by removing the gate drive from either the current or the output voltage. 

So design two circuits, one for voltage and one for current sensing that can control the pass transistor.  Then combine them through diodes so either one can reduce the output but both are required to increase the output.
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Offline bsodmike

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Re: Here's my schematic to prevent over-charging a capacitor, help please.
« Reply #15 on: April 15, 2021, 02:30:55 pm »
Inrush is probably a poor choice of term for the issue this design will have.  Or maybe it is exactly the right term.  My point is you are charging a cap, so by definition if you apply a voltage source it will have an arbitrarily high current at first and must be limited.  Your resistor does that.  But it charges at ever lower rates as the capacitor voltage rises.

I saw a design here not too long ago that used an op amp for each part of a current/voltage regulated power supply, which is what you need.  It used separate op amps to sense the current and voltage on the output and combined them with diodes in a way that allowed either to limit the output.  That is essentially what my circuit does by removing the gate drive from either the current or the output voltage. 

So design two circuits, one for voltage and one for current sensing that can control the pass transistor.  Then combine them through diodes so either one can reduce the output but both are required to increase the output.

Yes, when you said inrush, I understood as the high current draw into the capacitor - so I think that's a valid use for that term :)

Hmm, this is starting to sound like a similar design to a bench PSU, i.e. you can set a voltage limit and it can also go into CC (constant-current) if that limit is set.  I recall this project by Martin, and it's possible this could be adapted for the task:

 

Offline gnuarm

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Re: Here's my schematic to prevent over-charging a capacitor, help please.
« Reply #16 on: April 15, 2021, 03:43:08 pm »
What is it about the transistor based approach you don't like?  That would seem to be the simple approach.  if you use a Zener diode as the reference the reverse voltage issue on Q4 BE goes away as the Zener can't source current.  In simulation a BZX84-A10 zener gives an end voltage on the cap of 9.999V.  Of course the Zener has some tolerance built in. 

If you want to use op amps in this circuit, drive the base of Q2 from an op amp.  Connect the inverting input to both the output and Q2 base, the non-inverting input to M1s.  You will need to choose an op amp with rail to rail inputs and outputs.  A slow device will help prevent oscillations.  I don't think this op amp will add much to the operation of the current limit.

Q3 can be driven by an op amp replacing Q4 and D2 with the inputs connected to Vbb and Vref, observing proper polarities.  Non-inverting input should be driven by Vref and the inverting input driven by Vbb I believe.

You could use diodes on the op amp outputs instead of the transistors, but not much difference really.  You want the op amps to be able to remove the gate drive to the FET, but not force it on.  The advantage of op amps is that they load the circuit very little and have no offset to speak of.  However, Q2 is also setting the voltage reference for the current limit, so you need to add a second diode to create a reference voltage for the current limit and the circuit gets more complex.
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Offline bsodmike

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Re: Here's my schematic to prevent over-charging a capacitor, help please.
« Reply #17 on: April 16, 2021, 04:59:30 am »
Hey @gnuarm, I'm looking at your transistor based design.  Could you kindly share these bits that I'm missing in LTspice please:
- PMPB13UP
- PBSS5540Z
- ZXTP2006E6.spice.lib
- cph6122_rev0.lib

Thanks!!
 

Offline gnuarm

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Re: Here's my schematic to prevent over-charging a capacitor, help please.
« Reply #18 on: April 16, 2021, 06:00:44 am »
Yeah, sorry, I always forget the models.  Q2 is not critical, in fact none of them are.  I was trying to optimize that design for minimum drop out voltage.  In your case you don't need to worry with that. 

I'm pretty sure you don't need the cph6122_rev0 file.  Delete the library include.
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