This circuit uses two transistors to do what the op amp and transistor are doing. The BE voltage of the PNP serves as the voltage reference for the current setting. This makes it temperature sensitive, but the addition of the Schottky diode helps to mitigate that in addition to preventing back current flow when the power source is off.
Be aware this circuit does not limit the voltage to the cap being charged. In this app I wanted to charge as close to the incoming voltage as possible.
Simple charging schematic
Simple charging plot
The gate drive to the main current handling FET Q1 is the voltage on R3. Current limiting is controlled by Q2 which pulls up on R3 as the current through R1 increases reducing gate drive and providing regulation of the C1 charging current. R3 in conjunction with the voltages across D1 and Q2 BE junction set this current. Ignore the comments on voltages, that is from a previous iteration and was not updated.
C2 with R3 set the start up ramp if you don't want the current to ramp up too fast (important in many semiconductor applications). R2 is the bleed resistor for C2.
Here is the same basic circuit with Q3 and Q4 added to give a voltage limit.
Voltage limited charging schematic
Voltage limited charging schematic
Q3 acts like Q2 to remove the gate drive from Q1, but under control of Q4. D2 and Q4 BE junction act as the differential inputs on an op amp to pass current on Kill as the C1 voltage approaches Vref. As Kill is pulled down Q3 pulls up on R3 removing gate drive from Q1 limiting the voltage on C1. Vc1 reaches 10.04V as the simulation ends. The reverse current flow when power drops is in the nA range.
I like this addition. Nothing wrong with using op amps or comparators. They can give very precise control over the various settings. But I like a nice, clean transistor design as well. It is much simpler to make sure you are not violating any specs. Speaking of violating specs, the Vbe on Q4 will go to -Vref when power is off which is more than most transistors are rated for. So be sure Vref is off as soon as power fails. Seems even if the power level is not high, reverse current on the BE junction alters the transistor characteristics... or so I've been told. Maybe a reverse diode across Q1BE is in order.