High Bandwidth Current Injector for Impedance measurements

[Jay_Diddy_B]

Snip ..

When I review error amp (compensator) design in DCDC converters, I always see multiple pole/zero pairs throughout the bandwidth. Can you elaborate?

This topic should really be discussed in at least three different contexts:

1) Current Mode switching power supplies. They have the general form that I have a have modelled

Dominated by the output transconductance and output capacitance
Dominated by the error amplifier

Modified by ESR zero,
Modified by noise filtering poles.

Most modern switching power supplies use this topology


2) Voltage mode circuits

These generally need the type III compensator to deal with the double pole in the output filter.

Output Filter - Double Pole
Error amplifier - low frequency pole, multiple zeros, HF pole for noise reduction

ESR zero

etc.

3) Various LDO designs

…

Regards,
Jay_Diddy_B

[Wolfgang]

... and now, to test the limits, make a complex regulator with several poles and see how close the method gets.
My prediction: If you find a single strong "dominant" pole, it works OK, if not, it produces nonsense.

[Jay_Diddy_B]

Hi,

This Bode plot shows how predicable the behaviour of the 2 Pole, 1 Zero circuit is:



(When I did this it reminded me of 35 years ago, when we used LOG LOG paper and straight line approximations to do loop design)

It is basically head towards 0dB on a two pole slope, at frequency X turn left take a 1 pole slope and continue heading across 0dB …

Regards,
Jay_Diddy_B

[Jay_Diddy_B]

... and now, to test the limits, make a complex regulator with several poles and see how close the method gets.
My prediction: If you find a single strong "dominant" pole, it works OK, if not, it produces nonsense.

In addition to this there is the issue of signal amplitudes:

The power supply that I am simulating is based on a 6A monolithic regulator.
The output impedance is 50m

So if the injector can inject 10mA RMS

We have a signal size of 500uV RMS at the peak, 350uV RMS at the -3dB points.

( I know my HP3577A can operate with 10 Hz bandwidth to shutout other signals)

Has anybody seen this technique being used with switching regulators?

Jay_Diddy_B

[Wolfgang]

For multi-Amp devices your injected current is way too small. What about ca. 10% of the load current ?
Then you can expect to see something sticking out of the noise.

To the extremes, if you have an FPGA with several 10Amps at 1.1V you really need to bang the part with some Amps to see an effect.
The injector must be almost soldered into the circuit to avoid parasitic inductances (every nanohenry counts).

[16bitanalogue]

This topic should really be discussed in at least three different contexts:

1) Current Mode switching power supplies. They have the general form that I have a have modelled


2) Voltage mode circuits


3) Various LDO designs

Thanks for the download. Converter design is still new to me, and I am certain there is a paper (along with hallway discussions) that go into details about where to place the poles and zeros. I presume since most designs implement current control mode and if (presuming) the poles zero design rule of thumb is that they are placed far enough apart then the Q(Tg) method is 'expected' to work. It's one of those boundary assumptions that is not spoken about and is locked up in Tribal Knowledge for those who live and breathe converter design.

I was at a company where the topology was a voltage control mode, multi-level converter for battery charging. Spoiler Alert - shit didn't work (lots of problems). Now I get to work with simpler designs - standard bucks and boosts and the majority of the topologies are current control mode, Type II transconductance compensator.

[wa8pzl]

I had some boards burned for this project, results not as pretty as the OP's, but can confirm that the capacitance, ESL and ESR measurements work.