High Current PCB question

[akshaykirti]

Hello,

I am still a beginner in designing PCB's and have only designed a handful of them. I had a quick question regarding amperage/heat dissipation.

The board is a 4 layer board with the top layer being ground and the bottom layer being 12v(Only for this particular segment). I had to connect a 5A Pinch Valve which would be controlled by a microcontroller. We sourced a FET which met our current requirement and isolated the high power circuitry from the rest of the PCB. My question is that if I directly place the components like I have in the images(On the copper Pour). How good will the heat dissipation be? From what I understand the current has a lot more copper to flow through as the trace width of the connections will be super wide.

The board works fine and I didn't see it heat up etc. We are spinning a new board so wanted to ask best practices for this particular issue.

I am still a newbie so if I missed anything let me know and i'll try my best to answer you guys.


The Ferrite on the schematic is to reduce noise to the microcontroller, the Capacitor is there to reduce inrush current if that happens. A standard diode to avoid back emf is also included.

I chose all the components to comply with the necessary current requirements,

Capacitor
http://www.digikey.com/product-detail/en/UVZ1V103MRD/493-1327-ND/589068

FET
http://www.digikey.com/product-detail/en/AOD2610/785-1349-1-ND/3060928

[T3sl4co1l]

Four layer?  I don't see any inner layers in the picture..?

A D2PAK device will do about 1W on its own, with a minimal footprint (which is as shown).  That's kind of scary hot, and won't include any headroom for putting it in a stuffy box, elevated ambient, etc.

It's a little better for four layer, assuming the inner layers are solid copper planes, but not by too much.

Better is to have 2oz on the outer layers (preferably, all four layers), pours connected to the drain tab, and stitched top to bottom with lots of vias.  With up to 2 in^2 (6.2 cm^2) of pour, top and bottom, you can expect 1-2W safely, maybe a few more with lower margin.

To improve it further, you can add an SMT heatsink, or heatsinking to the back side (so the vias provide a thermal path to it, plus a pad of thermal interface material), which will bring you up to maybe 10W.  If you're pushing more than 5W, you should seriously consider a THT part mounted to a heatsink.

As for current capacity, that depends on Rds(on) of the device, and any switching losses you might need to worry about.

Tim

[McBryce]

What environment is this to be used in? What's the housing? Does it have air flow? Are there other components heating the area? Without knowing the real conditions it's hard to give a complete answer.

It's a bit optomistic at the moment, there's not a lot of room for worst case.

McBryce.

[suicidaleggroll]

What voltage is the MCU driving the gate with, and at what frequency will it be toggling (if PWM or similar)?

[akshaykirti]

We already tested this out and it didn't seem to be getting that hot. We are not pulsing the FET and need to put it on for about a a min or two.

This is just the power section of the board and hence did not have any stuff on the middle layers. We are using the middle layers for signal routing for the micro etc. What we were more concerned about was the trace width and the traces being wide enough to carry around  4-5A current

It is a nice idea to also use the middle layers in this section atleast for more pours.

The system will be placed in temperature controlled room with temperatures at about 23-25C(73-77F) and will be in box with holes for ventilation.

The Vin for the plane is 12V and is the bottom plane. The MCU works on 3.3V and works fine with turing on the FET

[suicidaleggroll]

We sourced a FET which met our current requirement

...

I chose all the components to comply with the necessary current requirements

That's the wrong way to choose a FET.  Current ratings on FETs are ridiculous, especially for DPAK.  They pretty much assume the package is in a bath of liquid nitrogen and the junction to case thermal resistance is all that matters.

What you should do is start with your acceptable voltage drop and/or power dissipation and then back that all the way up to the required Rds(on).

1) Decide what is acceptable for the application (how much voltage/power can you lose in your FET and still get enough to your load)
2) Decide what is acceptable from a thermal standpoint (what is the total junction to ambient thermal resistance of the package you want, what is the operating ambient temperature, and therefore what is the maximum power dissipation to stay within the thermal limits of the device).
3) Take the lesser of those two numbers, and then back out what your maximum Rds(on) can be to stay below that level at your maximum estimated current draw.
4) Finally, find a device that gives you an Rds(on) that's below that threshold at the gate voltage you'll be using.

[akshaykirti]

Actual Board is attached..

Ok, yeah I picked the FET which essentially worked with our microcontroller and had the necessary current ratings.

[suicidaleggroll]

The Vin for the plane is 12V and is the bottom plane. The MCU works on 3.3V and works fine with turing on the FET

You sure about that?  Because the datasheet begs to differ, check out figure 5.  Rds(on) hits an asymptote at around 3.5v, 3.3v is off the scale.  Vgs(th) can be as high as 2.5v on that FET, you should be driving it with a minimum of 4v if you want every device to perform correctly.  At 3.3v you may have some that work fine and some that don't (excess voltage drop, overheating, etc.).

[akshaykirti]

Another thing I was concerned about was the current trace width which needs to be pretty huge for 5A, hence just used a pour.

@sucidealeggroll, Umm, the circuit worked pretty well. I saw that in figure 2 VGS<3V for the amperage and went with it. Am i missing something here?

[akshaykirti]

Also, According to Figure 1, @VGS = 3V, it can do ~10A? So yes, if the current is more than 10A I would require a larger VGS

[suicidaleggroll]

@sucidealeggroll, Umm, the circuit worked pretty well. I saw that in figure 2 VGS<3V for the amperage and went with it. Am i missing something here?

Yes.  As I mentioned before:

Current ratings on FETs are ridiculous, especially for DPAK.  They pretty much assume the package is in a bath of liquid nitrogen and the junction to case thermal resistance is all that matters.

Do not use current ratings on FETs, they're pointless.  Use the acceptable voltage drop for your application, the acceptable power dissipation given operating environment, heatsinking, and junction temperature, and then back out the required Rds(on), and find a device that will hit or beat it by a good margin at your Vgs.

You don't even know what Rds(on) is for that FET at 3.3v, because it's not in saturation yet at that voltage, it's still in the linear region which will vary dramatically from device to device.

[akshaykirti]

Thanks for the advice. I will integrate another FET into the system. I'm meeting an electrical engineer for dinner so will chat with him some more. I just started with design engineering and am still figuring out stuff as i move along. I graduated with Computer Engg. so mostly know firmware/micro controller stuff well enough.

I have learnt from time to time that datasheets lie.

Back to my previous question? As trace widths are now pretty huge as I am using a pour for the power section; I hope traces won't be an issue?

[suicidaleggroll]

Also, According to Figure 1, @VGS = 3V, it can do ~10A? So yes, if the current is more than 10A I would require a larger VGS

You're grabbing the wrong information from that figure, you're reading it backwards.  What that figure is telling you is that with a Vgs of 3V and an Id of 10A, you'd have a Vds of 2-3V.  That's 20-30W being burned off in the FET, which would destroy it immediately regardless of how much heatsinking you have.

[suicidaleggroll]

Thanks for the advice. I will integrate another FET into the system.

I think that's a good idea.  It should be very easy to find a FET that will give you single digit milliohms of on-resistance at Vgs=3.3, so power dissipation will be a non-issue.  These FETs generally have very high gate capacitance which would limit their effectiveness for high speed switching applications, but that's not an issue here.

[akshaykirti]

I think i'm going to go with something with specs like this...

http://www.diodes.com/datasheets/ds31959.pdf

It seems to have a low enough VDS(0.1V) at ~5A and a realistic Rgs (It is given @2.5V). So the power dissipation on this should be pretty low at 5A(Around <0.5W)?

Thanks a lot for the help

[suicidaleggroll]

That's not much better.  According to Figure 1, at Vgs=3.3 and Id=5, Vds~=0.2.  That's 1W, that's a lot for that package.

You can do much better than that for DC operation.  Just go to digikey, find the Nch FETs in the package you want, limit it to ones with Rds(on) < 10mohm and Vgs(th) < 1.7v, and pick almost any of them.  Here's one right off the top of the list:
http://www.irf.com/product-info/datasheets/data/irlr6225pbf.pdf

Fig 12: Vgs=3.3 gives an Rds(on) between 3.5-5 mohm.  At 5A that's 88-125mW dissipation depending on temperature.

[akshaykirti]

Cool, I see that you de-rated it quite a bit. I noticed that the thermal resistance for the FET i mentioned was 72.9C/W and it's power dissipation is 1.72W; It could get decently hot. By how much do you recommend as a rule of thumb to derate this power dissipation?

[Siwastaja]

When used for low-frequency switching (almost DC operation, or tens of Hz), just pick an overly huge FET to eliminate losses almost completely and be done with it.

As stated before, you really need to work backwards from your thermal point (and possibly, acceptable efficiency, i.e., voltage drop to the load) to find maxium acceptable Rds(on), but sometimes the current rating is easier to find in the datasheet for the first-order device selection; in that case, the rule of thumb I use, is:

Absolutely necessary derating is: double the current rating, i.e., 10A part for 5A load.
For extremely low frequency switching (< 10Hz): preferably use at least 5x the current rating, i.e., a 25A part. Even 10x derating makes a lot of sense.
(This rule only works if you use the gate voltage that the FET really needs for proper switching, i.e., the curve that doesn't "level off").

The nice thing about FETs is that they have no bottom limit for decreasing conduction losses; you'll get asymptotically nearer to 100% efficiency and no losses at all. So if you have the money to buy a large $1 FET instead of a cheap $0.20 part, just do it. You can get away with no thermal design whatsoever, and still get something ridiculously fancy like a 5 degC temperature rise.

For fast switching, it's not so easy; the larger FETs will require stronger drivers. Driving them from just a microcontroller pin will cause much MORE losses (compared to a small fet) every time it switches, and that will become the killer in kilohertz range.

Another thing about FET selection is the maximum voltage it can switch, i.e., maximum Vds. As a rule of thumb, you need double the voltage that you'll switch. It's not that datasheets usually lie, but due to real-world effects like wire inductance, you'll have voltage spikes much higher than your actual voltage, and you can verify it with high-speed oscilloscope. Anyway, the thing is, the higher the maximum Vds rating, the harder it will be to find FETs that switch properly with low gate voltages! If you only have 3.3V, you are pretty limited to 20V or maybe 25V FETs, which will limit the switched voltage to 12V and even then you really need to do it right. With 5V, you could go up to 30-40 volts in FET rating.

OTOH, slow switching helps with voltage spikes, so the MCU pin driving the gate may actually be a good thing. But add a series resistor approximately matching the MCU pin equivalent resistance to prevent ringing. Something like 47 ohm will stop ringing without slowing down it too much.

If your load is a mechanical valve (a coil), it will require a freewheeling diode in parallel. But it probably already has it, given that your FET hasn't blown already.

Also, as a general rule, datasheets include those minimum/typical/maximum values; in addition, they often provide separate data for different temperatures. Always find the worst case for your calculation, sometimes it's the "minimum", sometimes the "maximum". For example, FETs increase their Rds(on) at higher temperatures, and at the same time, allowed heat dissipation is lower. Both of these work against you at the same time.

[T3sl4co1l]

We already tested this out and it didn't seem to be getting that hot. We are not pulsing the FET and need to put it on for about a a min or two.

This is just the power section of the board and hence did not have any stuff on the middle layers. We are using the middle layers for signal routing for the micro etc. What we were more concerned about was the trace width and the traces being wide enough to carry around  4-5A current

It is a nice idea to also use the middle layers in this section atleast for more pours.

The system will be placed in temperature controlled room with temperatures at about 23-25C(73-77F) and will be in box with holes for ventilation.

The Vin for the plane is 12V and is the bottom plane. The MCU works on 3.3V and works fine with turing on the FET

Ewww, no it doesn't.  The MOSFET is guaranteed for "logic level" operation at 4.5V, not 3.3V.  See Figure 5 in the datasheet.  It may be "on" enough at 3.3V, in a single test, but that is a special case.  If you put this in production, you will find some boards malfunction, or work intermittently as their temperature changes.

Also, avoid signal traces facing the switching node.  You don't want capacitive coupling to that.  Inner layers are best used for ground and power; signals naturally belong on the outside, being easier to route for SMT, and easier to deal with for prototyping.

Tim

[akshaykirti]

Thank you for the advice for selecting the FET guys. I believe where I was going wrong was interpreting the datasheet. I believe I've figured this out and will have a better design moving forward.

@tim We were using a Ground S S Power stackup as it performs slightly better for EMI. Right now I'm thinking of moving the ground plane to the bottom and the power plane up to avoid any breaks in the ground because of SMT components. We may also stitch Via's on the top and connect them to ground to have a faraday cage.

[Christe4nM]

Regarding EMI; you have a nice moat on your PCB surrounding the island where your FET is, yet you have several traces crossing that moat. I don't know your schematic and layout specifics of course, but it really stands out to me as that is in general a recipe for trouble. Of course I might be wrong and we're looking at two power sections instead of an isolated section.

[akshaykirti]

Here is the Voltage drop data i captured. Mostly looked at what kind of a power dissipation i would get as heat. I clearly see that this FET was a bad design choice(and this is why prototyping is important!). I also sort of touched the FET and it got pretty hot around 2.9V Vgs(I couldn't touch it).

I can clearly see that it would not be really good at the power dissipation and eventually just fail. The absolute Max power dissipation for FR-4 2Oz copper seems to be 2.5W and @VGs= 3.3V the dissipation was 2.2W.


Fet Datasheet
http://aosmd.com/res/data_sheets/AOD2610.pdf

Data collected
https://docs.google.com/spreadsheets/d/1Yg-FocEuL07Mt-szT3jVwBX5uytcRLMqMwQUjT45Rtc/edit?usp=sharing

@Christie Wherever the trace is going outside we have put a ferrite beads to reduce noise. We are also using linear regulators to further reduce EMI(Albeit at the cost of heat). The other thing going out is a 12V and Ground traces for the microcontroller pour. These are also passed through ferrite beads. Let me know if you have any other suggestions as we are going to spin a newer board with a couple of other things too. Attached is the Layout for this board.

[Siwastaja]

FETs are nice because they almost always have the same GDS pinout, so you can just change the FET without any redesign. FETs are also nice as you can parallel them. Sometimes even a kludgy installation of two fets soldered on the top of each other can do wonders, if you don't have a proper replacement in your hands.

But you should really use the gate voltage which doesn't have a flattening curve in the curve set.

Your application is a bit demanding for the FET, because you are switching a 12V load, which may be inductive, with a 3.3V gate. I wouldn't use a 20V part, but if you look at 30V parts, you simply cannot find one which is really on at 3.3V gate, so you need to derate even more.

An additional RC snubber over the FET might be a great solution and might enable the safe use of a 20V FET, especially as you are in almost DC operation and thus won't be adding losses with the snubber.