74161 sanity check

[slateraptor]

In need of a quick sanity check. HI/LO refer to voltage levels. Assume solid signal integrity and appropriate setup/hold timing.

CURRENT STATE:
CLRn  = HI
LOADn = HI
D     = don't care
ENP   = LO
ENT   = HI
Q     = 13

Given the references below, what is Q_next?

REFERENCES:
TI 74'161 Datasheet
TI 74F161A Datasheet
Some random generic 161 VHDL model from Mentor Graphics courtesy of Google

[magetoo]

Given the references below, what is Q_next?

I happened to have the "TI Logic Guide" open, and it has a function table for the '161 that says "no change" for that case.  (That's technically not what you asked, but...)

[slateraptor]

Unfortunately, I made the critical mistake of assuming a 74161 is a 74161 is a 74161.

Turns out the Signetics variant does not operate in precisely the same manner as the linked VHDL description.

This problem succeeded in driving a colleague and I batshit crazy for a week. After factoring out signal integrity and test code as possible culprits, I dropped all assumptions and tested the chip's behavior manually. What I observed was that when ENP was transitioned HI-to-LO while CLK was LO, the counter would increment once on the following clock cycle before holding count.

I immediately thought, "...gotta be counterfeit lot. Surprise!" Turns out after finding the Signetics-specific datasheet, the caveat was indirectly in the fine print:

(b) The HIGH-to-LOW transition of CEP or CET on the 74161 and 74160 should only occur while CP is HIGH for conventional operation.

Based on the quote above, the behavior I observed is technically undefined. TI's datasheet makes no mention of this whatsoever (although their timing diagram is consistent with the Signetics caveat).

Lesson learned. I wonder how many bugs were a result of this subtle nuance.