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High side Vgs oscillating back to 0V in miller region
uer166:
Some changes/results!
Changes:
* Added parasitic inductance in switch path
* Added peak voltage snubber
* On low side made gate discharge 5 Ohms with diode
* Set dead-time of low-high transition to -10ns (0ns would still turn on body diode freewheel, -10ns seems just about right!)
There is still no clean miller plateau unfortunately :'(, but high side gate doesn't go as crazy as before. The high-low deadtime is set to 90ns, and there's some interesting oscillations there still (~56Mhz), see last screenshot.
Edit: some good things came out of it though, like peak shoot-through current is only 16A, while it used to be 60A because of reverse recovery and lack of the parasitic inductors.
T3sl4co1l:
Your Miller is here:
It looks weird because the system isn't as, well, linear as you are used to. :)
If you mentally fill in the valley with equal flux (area under the curve) from the peak, that's where the plateau is. The voltage overshoots partly due to inductance (you're seeing Vgs + d(Id)/dt * Ls, more or less) and partly because Vgs really is overshooting, because of course it is, it's drawing peak current in that instant.
Where I've drawn the line is, ehh, it's probably a bit higher than the actual equivalent plateau, but around there.
Tim
uer166:
Ah I see. So I mean, the actual real question I have is whether there's anything wrong with it doing that in real design. As far as I can see all the abs. max ratings of FETs are respected, and nothing too crazy. So it "should" work just fine. The inverter hits 98.5% efficiency in sim, slightly over target (but will be brought down by shunt resistors) ^-^
duak:
One of my colleagues designed a similar circuit and found that he needed to add some gate to source capacitance to reduce the contribution from the Miller effect to reduce an EMI problem. It's not shown on the datasheet, but the transconductance of this device must be very high. Intuitively, any anomalous voltage coupled to the gates could cause trouble. I would reduce the series gate drive resistor to 10R and start with a couple more nF between the gate and source and see what happens.
Is anyone here familiar with emitter follower circuits and their counterintuitive ability to oscillate with capacitive loads? I wonder if a similar effect also manifests here with the upper device being a source follower? I've done very little with Spice simulations. I think it might be instructive to do a small signal simulation of parts of this circuit to see if there are any VHF instabilities.
Best o' luck,
T3sl4co1l:
--- Quote from: duak on January 25, 2019, 04:29:50 pm ---One of my colleagues designed a similar circuit and found that he needed to add some gate to source capacitance to reduce the contribution from the Miller effect to reduce an EMI problem. It's not shown on the datasheet, but the transconductance of this device must be very high. Intuitively, any anomalous voltage coupled to the gates could cause trouble. I would reduce the series gate drive resistor to 10R and start with a couple more nF between the gate and source and see what happens.
Is anyone here familiar with emitter follower circuits and their counterintuitive ability to oscillate with capacitive loads? I wonder if a similar effect also manifests here with the upper device being a source follower? I've done very little with Spice simulations. I think it might be instructive to do a small signal simulation of parts of this circuit to see if there are any VHF instabilities.
--- End quote ---
If you talk about adding capacitance from gate to source, you have to take into account the fact that you aren't connecting to the gate and source internally as such -- that is, you have package parasitics inbetween, and these can be enough to oscillate, in a similar way to the above consideration. :)
In general, any low impedance attached to the gate needs to be considered; transmission line stubs included, which is why we normally put the gate resistor near the transistor, to raise the minimum impedance (at any frequency) that is seen by the gate.
Tim
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