Author Topic: High speed (DC-42.5MHz), low voltage (150-500mV) peak detector circuit  (Read 7120 times)

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Offline microbug

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I'm building a DDS based function generator (OpenGen). Since the output of the DDS varies from around 1V pk-pk at the lowest frequency to around 300mV pk-pk at the highest frequency (42.5MHz), I need some sort of AGC to ensure the output is at the right level. There is already an 8-bit attenuation network (max 25.5dB) going into a fixed gain (75) amplifier. The fixed gain, by design, is too high for the lower frequencies which have larger amplitudes, so I intend to have a peak detector which feeds into the ADC on the micro, which then calculates the appropriate (minimum) attenuation.

There is a 'fast settling' peak detector circuit in the OPA365 datasheet (screenshot attached), but I don't think it will work because the schottky diode will drop the peak voltage of 150mV with the smaller signals. Can anyone suggest a solution
« Last Edit: July 29, 2014, 08:10:36 pm by microbug »
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Offline David Hess

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I would use a diode detector compensated for forward voltage drop and temperature.  Page 24 of Linear Technology application note 61 and schematic 1 of the Tektronix SG503 are good examples.
 

Offline microbug

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Having though about it for a while, I think that the attached screenshot (I forgot the first time!) must be the type of circuit you mean. I'll find a dual diode (thermally bonded) package to use for the two diodes.

Thanks!
« Last Edit: July 30, 2014, 02:04:01 am by microbug »
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Offline David Hess

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That design will be way too slow.

There is a similar but much faster open loop circuit shown on page 76 of Linear Technology application note 67 but even it is too slow.
 

Offline dannyf

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AD603's datasheet has a 40db agc implementation (using two AD603s).

Same can be done with dual gate mosfets (<20db each stage).
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Offline microbug

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@dannyf, that will be useful; I was having trouble finding a solution for attenuation and this will solve that problem. However, I don't have an equation for calculating the required gain (there is a complex output filter on the AD9850 module) so I would prefer to do it by measurement. I don't see how the AD603 will help to adjust the gain automatically, so ideally I need a way to sense the peak voltage of the AD9850 output.

Why would the peak detector schematic I posted be too slow?  I was planning to use it with a higher bandwidth (dual) op-amp (e.g., OPA2365), if that would be the problem. If not, is there any way to make it faster?

Thanks for your help so far.
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Offline tom66

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Why would the peak detector schematic I posted be too slow?  I was planning to use it with a higher bandwidth (dual) op-amp (e.g., OPA2365), if that would be the problem. If not, is there any way to make it faster?

Think about what happens when the output is negative. The amplifier will go 2 forward voltage drops below ground, so it will require a fast slew rate rather than high bandwidth. The diode capacitance is also likely to play a role at high frequencies.
 

Offline microbug

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Well, with regards to the op-amp I have a spare THS3001 with a 6500V/us slew rate which would do the trick. The THS3001 is a single op-amp, but (do correct me) as far as I can tell the other one is only a buffer.

What about PIN diodes? Looking on Farnell, typical capacitance is 1-5pF.
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Offline dannyf

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I don't see how the AD603 will help to adjust the gain automatically

Read the datasheet and if it is still not clear, we can discuss.
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Offline GeorgeOfTheJungle

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Think about what happens when the output is negative. The amplifier will go 2 forward voltage drops below ground, so it will require a fast slew rate rather than high bandwidth.


I don't see how. Don't you mean 1 forward drop below Vin?
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Offline microbug

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OK, I can see that the dual AD603 implementation on page 18 of the datasheet controls the gain using Q1 and R8 with a constant current into the collector of Q1. CAV functions as a peak detector which determines the gain. However, I don't see how this could be useful to me without some external input and measurement because I don't know how the output of the AD9850 varies exactly, just that it does.
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Offline dannyf

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Quote
I can see that

Read the datasheet more carefully or build one so you understand how it works.

Quote
some external input

Not sure why you think you need some external output (other than the signal itself). That's just how AGC works.

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Offline microbug

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If I am going to use this amplifier to get any output frequency at the same amplitude (say, 1.5V pk-pk), then the algorithm for determining gain would be A = 1.5 / Vin pk-pk. However, I would need to convert this to dB for input, so it would be A = 10^(0.1 * (1.5 / Vin pk-pk)). Then, to get the differential VG voltage it is (A - 10) / 40 for the standard configuration. I don't see how I can do all of that in hardware.
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Offline dannyf

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I don't see how I can do all of that in hardware.

You probably want to understand how the AD603 works, particularly gain setting with regards to pin 1/2, and how Q1/Q2 work in that circuit - the datasheet goes into some pretty details about the workings of that circuit too.
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Offline microbug

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I think it would be easier to use a multiplier like the ADL5931 (datasheet). With this I only have to multiply two voltages together to get an output rather than messing around with dB conversion. If X is the input and Z is the output, Y = Z/X . However, I again cannot find a way to do this just using external op-amps / transistors |O.
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Offline mikerj

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If I am going to use this amplifier to get any output frequency at the same amplitude (say, 1.5V pk-pk), then the algorithm for determining gain would be A = 1.5 / Vin pk-pk. However, I would need to convert this to dB for input, so it would be A = 10^(0.1 * (1.5 / Vin pk-pk)). Then, to get the differential VG voltage it is (A - 10) / 40 for the standard configuration. I don't see how I can do all of that in hardware.

I don't understand what you mean by converting the input to dB, or why this would be required?  The AGC amplifier in the app note appears to do everything you need.
 

Offline microbug

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EDIT: @mikerj, I was confused, it's not required.

OK, having read the datasheet more closely I think I understand. The AGC example states that Vout is equal to the sum of VBE (which has a negative temperature coefficient) and R8 (which has a counterbalancing positive temperature coefficient). Therefore the peak to peak output will be about 2VBE.

I don't need much total gain for AGC (a few decibels at most), so I won't need a cascade configuration. I'll post a schematic in a while.
« Last Edit: July 31, 2014, 11:36:21 pm by microbug »
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Offline microbug

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Re: High speed (DC-42.5MHz), low voltage (150-500mV) peak detector circuit
« Reply #17 on: August 01, 2014, 12:32:37 am »
I have attached the schematic. I connected the FDBK pin to VOUT to allow the amplifier the negative gain it will require. I also took the capacitors on the input and on VAGC up to 1uF to allow lower frequency signals. DC still won't pass, but at least it'll go down to a few kHz now. It also runs on 12V (I have a very low noise 12V line for analog stuff already), although I don't think this will affect performance.
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Offline dannyf

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Re: High speed (DC-42.5MHz), low voltage (150-500mV) peak detector circuit
« Reply #18 on: August 01, 2014, 12:43:14 am »
Quote
I think I understand.

I would suggest that you read the (AD603) datasheet a few times more.

As a VGA, AD603 has an AGC range (not gain) of about 40db - Figure 4 of the datasheet. The gain is adjust, up or down, based on the voltage differential on GPOS(pin 1) and GNEG(pin2).

The circuit on Figure 49 is a cascaded AGC circuit - A1/A2, with their GNEG fixed and GPOS floating, driven by a peak detector formed by Q1/Q2 and Cav.

Q2 charges up Cav, and Q1 discharges Cav, based on the negative peaks on Vout: low Vout drags down Q1's emitter and opens a current path from Cav to A2's output, thus lowering Cav / GPOS.

Lower GPOS leads to lower gain for A1/A2, which reduces the negative peaks on Vout, which restores Cav -> forms an AGC loop.

R5/R6/R7 set up the gain for A1/A2.

Similar structure can be adopted for a dual gate mosfet as well, with smaller AGC range per stage. Or if you don't need as much AGC range, you can simplify it to a one step implementation.

Again, all of this is well explained in the datasheet. All it takes is for you to go through it one sentence at a time.
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Offline microbug

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Re: High speed (DC-42.5MHz), low voltage (150-500mV) peak detector circuit
« Reply #19 on: August 01, 2014, 01:36:02 am »
Thank you for explaining. I have read the AD603 datasheet many times already, but I have just gone through it again (especially the description of the AGC example) nevertheless, and I feel I understand the AGC circuit now.

Since my input will vary from ~300mV to ~1V pk-pk, I won't need much AGC range. Therefore I opted for a single AD603. My configuration is pretty much identical to that in the datasheet, but it is not cascaded and operates on 12V. Additionally, it has a larger input capacitor (1uF) to allow lower frequencies to pass (-3dB @ 16kHz) and I removed the 50ohm input termination as it was not needed. See the (revised) attached schematic.
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