High Speed Design Project for Highspeed Beginner

[nctnico]

Olimex has a nice range of IMX233 based boards. Its their answer to the Raspberry Pi.

[vvanders]

...

As things are now, it would be virtually impossible to design and market any kind of computing platform that could seriously challenge the existing status quo. Partly for technical reasons, but mostly because the lawyers would have your balls.
The obstacles are:
 - Can't use existing 3D graphics accelerator chips because nVidia etc refuse to provide opensource drivers.
 - Can't substitute the 3D engines and develop open-hardware processors with high-end FPGAs because the high end chips & tools are not available to unapproved parties.

MS-Windows has become such a pile of deliberately software crippled bloatware, that it would be quite feasible to design a hardware platform and OS from scratch, using much slower CPUs and other hardware, but which still gave better user responsiveness.
It's doing decent 3D graphics independent of TPTB that is currently the killer. It's an intractable problem , and seems to be getting worse as potential ways around the monopoly get closed off.

Not sure how true that really is TBH when you look at how the mobile market is going, stuff like Adreno and PowerVR are getting quite impressive. I don't think the market is nearly as cornered as you think it might be.

[yanir]

Olimex has a nice range of IMX233 based boards. Its their answer to the Raspberry Pi.

Thats how I discovered the proc. It's also used in the chumby hacker board. (also Bunnie designed).

[yanir]

No. The routing rules are quite similar, but with DDR1 you have the added complication of needing discrete termination resistors included as well - and you have to match the lengths of the traces taking both sides of these series resistors into account.

With DDR2 the termination resistors are internal to the chips, so you have to route and configure the ODT signal - but that's much simpler than having to include discrete resistors. With DDR2 you have a tree structure for the address & control bus, so you'll need to insert T points into your traces and ensure that each branch of the tree is the proper length.

Arguably DDR3 is easiest of all in terms of the PCB layout; it uses a 'fly by' topology which means the tree isn't needed, though there's more configuration and auto calibration to be done by your processor at boot time.

Andy, I am starting to route my board and I have been reviewing the freescale/micron data sheets and the development board gerbers ( which I have based my design on).

Here is what I see:
Freescale does not use termination resistors in their development board. They follow the suggestions in the micron app notes but ignore termination. In the freescale hardware design guidelines they refer to a Y layout for routing to 2 ddr chips. Is this the same as "balanced T" ? I cannot find reference to "Y" routing anywhere else.

Freescale suggests keeping the tracelengths for Datalanes, strobes and masks to under 2.25cm (885 mil) but it can be longer if multiple ddr chips are used. They site an equation based on FR4 dielectric material and rise/fall time of the signal to produce this value. They then say it can be longer for multiple chips but don't explain how to calculate.

3.3 Minimizing Reflections
Keep the DRAM DATA, DQM, STROBE, and CLOCK traces short enough so that a maximum of 30%
of the edge appears on the trace. Thus, in equation form,

Trace Length ? (0.3 × Rise/Fall Time × 15 cm/ns).

The speed of a signal edge traveling from sender to receiver on widely used FR4 material is about 1/5 the
speed of light (or 15 cm/ns).

The full reflection occurs if the time for an edge travelling from sender (i.MX) to receiver (DRAM) is ?
the rise/fall time of the signal. Example:
If the rise/fall time = 0.5 ns and trace length = 7.5 cm, the receiver still sees “0 V” even though the
sender is now driving at the maximum DRAM supply voltage. Because the full edge is now on the
line, full reflection occurs.

So for this example, the signal traces should not exceed 2.25 cm (30% of 7.5 cm). This is valid for
the distance between one sender and one receiver.
Note that this example calculation is for a point-to-point connection. If more than one memory device is
connected to the bus, the rise/fall time is slower, and the trace length may be longer.
Control signals like CS, ADDRESS, RAS, CAS, and WE are not critical and can be routed without these
constraints.

3.4 Routing to Multiple DRAM Devices
In terminated systems, “daisy chain” routing is recommended because the impedance can be matched
along the whole trace. In nonterminated systems, “Y” routing is much better because it makes the trace
lengths shorter, which reduces the capacitive loading.

I analyzed all of the data lanes trace lengths in the gerber for the eval board and the results are interesting:
DQ7:1 range from 1325mil to 1457mil (+/-136mil)
DQ15:8 range from 1553 to 1635 mil (+/- 82 mil)

This spread is more than the +/-50mil micron recommends.

I'm learning quite a bit, and I feel that If I implement my design according the micron data sheet without termination I should be ok, but I am still a bit uneasy about it.

Any thoughts?

[jeroen74]

Maybe the Freescale has internal termination resistors?

[yanir]

I don't think so, I couldn't find any mention of it in the data sheet and I've seen other designs that use series termination with the i.mx233. Also from what I understand you need to pick your termination values based on layout and simulation results so having fixed value termination would not help.

[AlfBaz]

Hi Yanir.

I am very interested in what you are doing. I have been messing around with a similar design but using DDR1 memory. I haven't built anything yet but have read tonnes on the subject and still feel a little lost. This plus the cost to get a finished prototype to the test stage has seen me shelve the project until I am a little more financial.

Please keep in mind with the following text that I’m only a dumbass electrician and in the words of our venerable host, I’m probably talking out my arse.

With regards to certain manufacturers boards and the apparent disregard for signal integrity rules you would have to take into account the considerable resources at the manufacturers’ disposal.

Firstly it would be nothing for them to get a few spins of proto boards with test coupons and then carry out tests with expensive equipment to verify the boards. They can probably afford to get tight impedance controlled tolerances on the boards and have access to signal integrity software with field solver capabilities so they can layout the board and then run extensive testing before they send for them.

[conspiracy theory] Secondly it wouldn’t be surprising if the design engineers have verbal access to the chip manufactures and conversations along the lines of “Yeah the data sheets say this but we have gotten away with as much as this, if you stay within that you should be ok, I’ll email you a more realistic ibis file” [/conspiracy theory]

With reflections there are at least two things that are needed for them to occur. As you have already quoted, if the rise/fall time of a signal is less than a third of the time it takes to get to its destination you’ll create a wave on the line with sufficient amplitude to create problems.

Secondly if there is a mismatch in energy transfer somewhere along that line (vias, receiver or more specifically a change in impedance) then a reflection will occur.

If you can imagine along piece of rope and you whip one end up and down, the wave created will travel down the rope, hit the other end and bounce back. Now imagine that half way along the rope we tie a thicker rope and whip it again. When the wave reaches the heavier rope some of the energy will be absorbed by the heavier rope and the wave will continue along it although at reduced amplitude. The remaining energy will bounce back along the first bit of rope.

Going back to the first example where the one piece of rope is tied to a fixed point this is analogous to a very high impedance or open circuit. If instead of tying the rope to a fixed point we place a spring vertically with the top and bottom of it anchored and tie the string to the middle of the spring and the energy required to move the middle of the spring was equal to the energy in the wave coming down the rope, the spring would absorb that energy and the amount of reflection would be proportional to the mismatch in energy transfer other wise no reflection will occur

If you are able to match the drivers’ output impedance with the trace and the receiver then regardless of how long the trace is you shouldn’t need to add termination resistors to match impedances

With lengths being matched to each other this more to do with data arriving at the same time to avoid skew and thus data corruption.

You probably know all of this but I wanted to put it out there to see if my understanding is sound

[yanir]

You probably know all of this but I wanted to put it out there to see if my understanding is sound

I don't know as much as you think. I this is my first DDR based layout and to make things "foolproof" I'm sticking very closely to the dev board design (As far as DDR is concerned).

The Freescale app note stresses layer and via matching over trace length. I'm still going to follow what micron states though.

Your impedance matching analogy is great and really helped me visualize a confusing and often poorly explained concept.

Good luck with your project, it is expensive to produce my board at proto quantities (luckily I'm not paying for it .

You should check out the chumby hacker board and the oilmex olixuino. They both use a 4 layer board so it's not as expensive as the recommended 6 to produce. Both projects are well documented and open source hardware.

[marshallh]

You don't need series termination for DDR1 when using one discrete module. (Bare chip). Micron says this themselves in one of their appnotes. Read them all.
This however is contingent upon your trace lengths staying short (1-2inches max) and no stupid routing mistakes.
For longer traces it's good to put in midpoint termination. This is because the DQ bus is bidirectional. Treat DM/DQS just like the data lines. All other signals are running at half the speed and are less critical. I have done pcbs with both setups and they worked fine, though at just 266mhz tested.

DDR2 is even better for point-to-point connection (i.e. connecting one ram chip directly to your contorller). They have on-die termination BUT this is only for data the module is driving. You will need corresponding controllable source terminations on the controller outputs. I.e.Cyclone 3/4 OCT output termination.

[yanir]

You don't need series termination for DDR1 when using one discrete module. (Bare chip). Micron says this themselves in one of their appnotes. Read them all.

Thanks I'll try to find it. This design uses 2 discrete modules. Do you think that still applies?

[AndyC_772]

Andy, I am starting to route my board and I have been reviewing the freescale/micron data sheets and the development board gerbers ( which I have based my design on).

Here is what I see:
Freescale does not use termination resistors in their development board. They follow the suggestions in the micron app notes but ignore termination. In the freescale hardware design guidelines they refer to a Y layout for routing to 2 ddr chips. Is this the same as "balanced T" ? I cannot find reference to "Y" routing anywhere else.

I'd assume it's the same thing, route from the CPU to some point on the PCB, then from that point to each of the two DDR chips. Keep the lengths of the branches of the Y the same as each other.

Freescale suggests keeping the tracelengths for Datalanes, strobes and masks to under 2.25cm (885 mil) but it can be longer if multiple ddr chips are used. They site an equation based on FR4 dielectric material and rise/fall time of the signal to produce this value. They then say it can be longer for multiple chips but don't explain how to calculate.

I'm not surprised. The correct way to design a high speed interface like this is to simulate the layout with software like HyperLynx or the Cadence SI analysis software, which should fairly accurately predict the behaviour of the interface once it's been routed. The layout process is iterative: start with something that looks sensible, simulate, check timing margins and signal integrity, then modify the layout and try again. Keep going until you have a board that works.

Freescale, like other manufacturers, has no doubt done this and tried to provide some rules of thumb for other designers who don't have access to these tools - but it's not as simple as "plug these figures into this formula and you'll get something that works". They'd be oversimplifying the problem if they even tried.

I analyzed all of the data lanes trace lengths in the gerber for the eval board and the results are interesting:
DQ7:1 range from 1325mil to 1457mil (+/-136mil)
DQ15:8 range from 1553 to 1635 mil (+/- 82 mil)

This spread is more than the +/-50mil micron recommends.

I'm learning quite a bit, and I feel that If I implement my design according the micron data sheet without termination I should be ok, but I am still a bit uneasy about it.

Any thoughts?

People can get a bit hung up on length matching. With DDR2, the length matching is important in order to ensure equal delay and capacitive loading between each data bit and its associated strobe. This ensures that they all transition together at the receiver, which means there's no added clock-to-data skew that will reduce worst-case timing margins. However, if you work out the actual propagation delay involved in that 136 mil of track, I very much doubt it's significant really.

[yanir]

Update, I just got my boards a few days ago and I've been testing for the past two days. I am happy to say that it boots! Memory appears to be working great (or adequately for booting at least ).

Thanks for everyone's guidance. Here are some images of the DDR1 layout:

[cwz]

Another interesting thing was that while getting the boards manufactured overseas (they worked) we were told by the PCB makers that there's _another_ even more strictly controlled level of secret Intel docs, that only the biggest, approved makers of Intel motherboards ever get to see.


There are other associated stories. Such as what happened to the availability of JTAG CPU emulator/debuggers for Intel processors, and the true purpose of SMM. But thats for another day.

What you're describing is what they call "red cover" access -- what you've shown here is "yellow cover".  It's not really any sort of conspiracy or anything like that.  As you noted, their primary goal is to sell chips, and as such, they have limited resources for doing things like design review etc.  As I'm sure you're aware, doing an actual, involved design review takes considerable amounts of time and resource.  Thus, they can't offer it to everyone.  Clearly, they're not going to spend time for hobbyist projects, and in many cases, not for stuff that companies are running less than several thousand pieces of, because there's just not enough margin in it for them to have it make business sense.

So it follows that they don't give out sensitive documentation readily to anyone who asks for it, because there's no reason for them to take on that level of exposure for things that aren't going to go anywhere.
Also, they have to consider who they're giving it to and what their level of recourse is should it happen to leak.  Basically, when you're given red cover access, you agree that should the documentation happen to leak, you are causing them an exceptional level of damage, and that they're entitled to come after you.  Of course if you're a smaller company, in most cases, that doesn't add up to much.

Anyhow, that's basically the deal with this stuff.

FWIW, you can still get Intel JTAG debuggers from Wind River and American Arium.

[marshallh]

Nice one on the routing, but is this 4 or 6 layers? You are really missing a solid reference plane here. That is going to cause you more SI issues.

[yanir]

Nice one on the routing, but is this 4 or 6 layers? You are really missing a solid reference plane here. That is going to cause you more SI issues.

Thanks!

It's a 6 layer design. I have a solid gnd plane a power plane split up for the 5 different rails. The VDDM (2.5v) rail is a solid plane under (and surrounding) the memory.

[marshallh]

Thanks!

It's a 6 layer design. I have a solid gnd plane a power plane split up for the 5 different rails. The VDDM (2.5v) rail is a solid plane under (and surrounding) the memory.

Good on ya. You should have zero problems with the ram (I've done much worse and had things still come in working).
I dont' recall what Vref source you used, but for only a few discrete modules a resistive divider will work fine. Two 5% 1k's is enough. They do this in commodity designs using DDR1.
Don't use a vanilla LDO because it will not properly track changes in Vddm. Purpose-designed DDR Vterm/Vref regulators have both a tracking input and regulator input.
I've used a LP2995, TI3012, and resistive divider and all worked.

[AndyC_772]

If you use a resistor divider, check the maximum Vref current that the DRAM devices can draw, and make sure your voltage output remains within spec under those conditions. I've had to use surprisingly low value, not to mention accurate, resistors for this purpose before.

Also, for the record, you should really try to ensure that your high speed DRAM signals don't cross breaks in their adjacent power or ground planes. Crossing a plane break introduces an impedance discontinuity, which can result in reflections occurring and reduced SI. Often boards with high speed DDR interfaces on them require more planes than they otherwise would for this reason.

As it's DDR1, did you not need series termination resistors in between the CPU and memory IC?

[yanir]

I dont' recall what Vref source you used, but for only a few discrete modules a resistive divider will work fine. Two 5% 1k's is enough. They do this in commodity designs using DDR1.
Don't use a vanilla LDO because it will not properly track changes in Vddm. Purpose-designed DDR Vterm/Vref regulators have both a tracking input and regulator input.
I've used a LP2995, TI3012, and resistive divider and all worked.

I used a voltage divider as in the reference design. It's a 1K 1% divider with parallel 0.1uf bypass capacitors.
Thanks for the tip on the vterm/vref regulators, i'll be sure to look into those.

If you use a resistor divider, check the maximum Vref current that the DRAM devices can draw, and make sure your voltage output remains within spec under those conditions. I've had to use surprisingly low value, not to mention accurate, resistors for this purpose before.

I'll check.

Also, for the record, you should really try to ensure that your high speed DRAM signals don't cross breaks in their adjacent power or ground planes. Crossing a plane break introduces an impedance discontinuity, which can result in reflections occurring and reduced SI. Often boards with high speed DDR interfaces on them require more planes than they otherwise would for this reason.

Yes, I've read that and the VDDM plane is contiguous under most of the BGA all the way to the memory modules. The data lines do not cross any splits.

As it's DDR1, did you not need series termination resistors in between the CPU and memory IC?

The schematic for the reference design I was using did not include any so I opted to stick to it. I did review another similar design (chumby hacker board) that used series termination with a different brand of memory. I stuck with micron and the same part in the reference so I thought it was a safe bet. I also didn't have access to simulation so I wouldn't have been able to adjust the values.

Fortunately it worked.