EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: yanir on December 11, 2012, 09:50:09 pm
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Hi, I'm designing a product that will utilize an ARM based processor (http://www.ti.com/product/am3352 (http://www.ti.com/product/am3352)). It's a pretty powerful and inexpensive (at volume). This will be my first ARM based project and first truly highspeed project as well. I will use DDR3 memory for as well (I am basing the design off their reference design).
I've done Highspeed usb designs and RF module designs with microcontrollers running 8MHz to 12MHz. I think this should go well, and I've read up on high speed layout for such devices. Just wondering if anyone thinks this requires more experience to do properly?
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Just wondering if anyone thinks this requires more experience to do properly?
Maybe, but what better way to gain that experience than by trying for yourself?
Make sure to use a 4 layer board and be familiar with the following when laying out your traces:
http://en.wikipedia.org/wiki/Microstrip (http://en.wikipedia.org/wiki/Microstrip) (for controlling the impedance of your traces)
http://www.mantaro.com/resources/impedance_calculator.htm#microstrip_impedance (http://www.mantaro.com/resources/impedance_calculator.htm#microstrip_impedance)
http://www.mantaro.com/resources/impedance_calculator.htm#differential_microstrip2_impedance (http://www.mantaro.com/resources/impedance_calculator.htm#differential_microstrip2_impedance)
Also, make sure you use correct termination for your differential signals:
http://www.micrel.com/_PDF/HBW/other/Micrel_HBW_Termination_Techniques.pdf (http://www.micrel.com/_PDF/HBW/other/Micrel_HBW_Termination_Techniques.pdf)
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Thanks for the encouragement! I agree, its for work however and there is a deadline. So the pressure (self inflicted) to deliver results will be high on something new. But the challenge and learning something new is what excites me.
I'll review your links, thanks for sharing.
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I believe DDR3 needs 8 layers, not 4. From the several documents I read, it's absolutely not trivial at all. Endless checklists and such. Just Google for DDR3 layout guidelines and several papers turn up.
I wish you good luck! Do you have any equipment at your disposal to debug this properly?
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The reference design is indeed 8 layers.
This processor supports DDR1 and DDR2 so I am considering moving down if my application will run nicely on those memories. I am also looking at less hefty ARM solutions.
As far as my equipment goes I have a TEK TDS1002B 60Mhz 1GS/s scope, so an upgrade is in order. I was thinking of getting an Agilent 3000x 1.5Ghz. Would that be cutting it too close to look at DDR3 signaling?
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Actually probing DDR interfaces in a way which yields accurate, meaningful results is, frankly, so costly and involved a process that you're better off not bothering at all. You need, at an absolute minimum, a scope and an active probe with a bandwidth 10x greater than your clock frequency, and to do it properly you're in the realm of specialist adapters and solder-in headers. Budget thousands just to rent the kit for a week or two.
Most of us don't bother, though. Simulation, using a tool like HyperLynx or SigXplorer, is a better bet - though even then you'll be renting the tools or hiring someone who has them. The practical solution to DDR routing is to follow the layout guidelines which the CPU manufacturers give out, follow them to the letter, and then test your product thoroughly. There are various timings which can be programmed, so start with values which you believe should work, and then adjust them either way to find the valid window which works. You can then pick a value near the middle of that window and know that you have reasonable margins.
Laying out a board for DDR3 with just a few chips on it isn't all that complex in signal integrity terms. It only gets really bad when you start using plug-in DIMMs, and especially, more than one plug-in DIMM. If you're designing PC motherboards, for example, then you really do need expensive simulation tools.
The biggest headache can be programming up the DDR memory controller in the CPU correctly. Don't be surprised if it looks daunting; I've been hired professionally just to do this for a company before now.
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I saw some of those those intimidating checklists mentioned.
TI addresses this in their DDR3 Doc here: http://www.ti.com/lit/an/spraav0a/spraav0a.pdf (http://www.ti.com/lit/an/spraav0a/spraav0a.pdf)
Basically they say that although DDR3 layout is still not trivial they demonstrate a rule based approach that a designer can follow.
Andy this seems to agree with your what you say. Follow the manufacturers guidelines to a letter. I plan on using a single chip and am stripping down the reference design to remove unwanted peripherals. TI has released the BRD file which I'm reviewing. There is quite a bit going on but it doesn't look too bad. I just want to make sure my board will boot on the first spin!
Andy If I use their supplied linux/android distributions on my board will I have to program the DDR controller much?
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If you're familiar with rf design and signal integrity (length matching, controlled impedance, propagation delays and the like), then provided you follow the design rules given by the manufacturer you should be fine.
There will be things which only you know about your design: the amount of memory, the width of the address and data buses, the clock speed, the speed grade and manufacturer of the DRAM devices you're using. You'll need to either program up the DRAM controller yourself to match these, or to configure the pre-existing driver if you're using one. Hopefully the author of the DRAM driver code will document how this is done and what parameters can be configured.
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Designing fast memory busses comes down to keeping the data and DQ lines of a lane equal in length and try to route all the data signals on the top layer. It usually requires quite a bit of work (planning) to order the data lines and lanes so you don't need vias. Sometimes it helps to use a larger BGA packages so its easier to route the data lines away from the processor on the top layer. The next thing are the control lines. Make these equal in length as well but they are not so sensitive because they operate at half the clock speed so using vias is not so critical. There may be length requirements / limits in the routing guidelines. You need to adhere to these closely. Forget about microstrips. There isn't enough room for those.
These kind of projects usually can be routed on a 6 layer board if you plan the design carefully. IOW think about how the PCB layout is going to look like (including the copper pours for the power planes) and which power supplies can be combined before drawing the schematic.
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Back in 2006 (?) I was involved in a design of an Intel P4 board. The specs for impedance control of many signal lines such as the high speed serial between CPU and northbridge, are extremely tight. That was where I first used a HP 54121T - the TDR capability allows measurement of PCB trace impedance and variation along the trace. It's so sensitive you can see a bump just from holding your finger _near_ the trace.
Much to our dismay, we found that all the Australian PCB manufacturers we tried were unable to achieve the manufacturing tolerance that the chips specs required. We had to have the boards made overseas, in SE Asia.
What was most disturbing was that Australian board makers didn't have the ability to qualify trace impedance directly, and most didn't seem to even understand the concept. May have changed now.
We learned a few other interesting things about Intel CPU designs too. The yellow books, <cough>.
A fine example of why I think corporations can never be trusted. Hey, I should tell that story, to enlighten those who seem to think such bastardry can't possibly happen. Wonder if I'd get sued?
I hope you don't have similar problems with your ARM design. If you do need to measure trace impedance, try one of these: HP N1020A TDR probe - PCB probing for 54121T. They work very nicely.
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One of the big issues I can see at high speed is controlled impedance. Especially if you work in a large company and the purchasing department decides to swap PCB manufacturers cos "they are all the same aren't they?" |O
Neil
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Or when you forget to specific the thickness of the PCB if it's not the standard 1.6mm :)
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Many traps for young players such as myself! I will be sure to heed all the helpful advice here. I ended up switching to a different processor (freescale i.mx233 series). It uses DDR1 only. The speed is significantly lower (133MHz or 167Mhz). Is this more forgiving or are routing rules just as strict?
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The most important aspect is flight times, clearly higher freqencies will need smaller transition times to allow the signal time to settle to a loginc high or low ( keep the eye open) but you need to see what options you have with regards to drive stength, rise and fall times. This stuff can be so anal that you have to consider the uneven distances from chip die to chip pins
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Many traps for young players such as myself! I will be sure to heed all the helpful advice here. I ended up switching to a different processor (freescale i.mx233 series). It uses DDR1 only. The speed is significantly lower (133MHz or 167Mhz). Is this more forgiving or are routing rules just as strict?
That should be much, much easier.
Speaking of traps, there are some you really wouldn't expect to encounter. Let me tell you the story of the Intel Yellow Books. Very briefly and vaguely, hoping that this won't bring down the legal harpies.
Most people would assume that a company like Intel would be all about selling chips. So you'd think the published CPU chip technical data books would contain all you'd need to produce working designs, and there definitely wouldn't be any deliberate lies or critical omissions in the data books, right?
WRONG!
It goes like this. You or your company starts work on a design. Based on published specs you choose Intel. You contact the Intel reps and ask for all available information, reference designs, etc. You get given all that, plus contacts for assisting with debugging your design. You begin the design. You hit some problems - there seem to be things just not right with the published docs. You enter detailed discussions with Intel, during which they review your design and learn all about your intended application.
At that point, IF THEY APPROVE OF WHAT YOU ARE DOING, they go "Oh hey, did we mention there are some other documents you'll need? Here they are. But they're very secret, don't tell anyone they exist. Or we will be very angry with you and you'll never get any further assistance or chip purchases from us, ever again."
That was in the period 2000-2008 (I'm being deliberately vague.)
It turns out it's flatly impossible to complete a working advanced Intel processor design without these documents. So what Intel is doing, is operating a strict gateway on who will be allowed to produce Intel CPU-based platforms.
If you're wondering why PC platform evolution seems so controlled, this is why. No disruption of the planned progression will be allowed.
Now, at this point you're probably thinking "Bullshit! Do you expect me to believe Intel would do such a thing? You damned lying conspiracy nut!"
OK then. A picture of some example yellow books. Hopefully with all identifying details, date, camera model, pixel imperfection map, etc scrubbed clean. It's an old, old pic, and I do not possess these documents and never did. I know nothing, no point asking me. Especially not names and company details. My memory is really terrible these days. But I do recall all these books had surprisingly low serial numbers. Not many ever issued, apparently.
[Hmm. How do you make an attached image appear within the text?]
Another interesting thing was that while getting the boards manufactured overseas (they worked) we were told by the PCB makers that there's _another_ even more strictly controlled level of secret Intel docs, that only the biggest, approved makers of Intel motherboards ever get to see.
There are other associated stories. Such as what happened to the availability of JTAG CPU emulator/debuggers for Intel processors, and the true purpose of SMM. But thats for another day.
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Barcodes also need to be redacted...............
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Oops! :palm:
Fixed.
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That is how John Macafee was done..........
Depends if the Googlebot scraped it in the interim as to whether it is still visible in a cached shot..............
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scan that shit ! :-+
It's very underhanded of them to waste your time like that. You need to put in all that effort to have them give you the possibility of approval....
That should be illegal.
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scan that shit ! :-+
Ahem... if I had the docs... that might get lots of people in serious trouble. Much as I'd *like* to stick one up Intel. _If_ I had the docs, which of course I absolutely don't.
It's very underhanded of them to waste your time like that. You need to put in all that effort to have them give you the possibility of approval....
That should be illegal.
I totally agree. But then there are lots of things in the present world that I think should be illegal, and other illegal things that shouldn't be. I don't have much hope of this mess getting better any time soon.
The really creepy part is when you start to look into why they do that. And connect dots with other developments, like the removal of CPU emulators from the marketplace (unless you're Intel-approved), hidden shit in the processors like the SMM activities (which you can't see without a hardware emulator, ha ha gotcha!), the ongoing efforts to make large scale FPGA development systems & chips unavailable to 'little people' (Xilinx has gone over to the Dark Side), Microsoft's self-admitted plans to 'close the box' to make DRM systems unbreakable (and lock out open source development and OSs from the PC platform) plus the near total patent-lock the 3D graphics accelerator chip makers have on graphics card development and software drivers now.
As things are now, it would be virtually impossible to design and market any kind of computing platform that could seriously challenge the existing status quo. Partly for technical reasons, but mostly because the lawyers would have your balls.
The obstacles are:
- Can't use existing 3D graphics accelerator chips because nVidia etc refuse to provide opensource drivers.
- Can't substitute the 3D engines and develop open-hardware processors with high-end FPGAs because the high end chips & tools are not available to unapproved parties.
MS-Windows has become such a pile of deliberately software crippled bloatware, that it would be quite feasible to design a hardware platform and OS from scratch, using much slower CPUs and other hardware, but which still gave better user responsiveness.
It's doing decent 3D graphics independent of TPTB that is currently the killer. It's an intractable problem , and seems to be getting worse as potential ways around the monopoly get closed off.
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I agree on the Intel story. I once had the idea of using an Intel Atom cpu in an embedded design. The sales reps came up with loads of questions and ridiculous prices ($50 per piece when buying 1000 pieces while some Chinese are selling complete Atom boards for $45).
To the OP: better go for the IMX51 or IMX53. IMX23 is no longer supported. Either way you'll need to adhere to the routing guidelines. And whatever SoC you choose: use Micron memory. I've tried other brands but those just won't work reliably.
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I agree on the Intel story. I once had the idea of using an Intel Atom cpu in an embedded design. The sales reps came up with loads of questions and ridiculous prices ($50 per piece when buying 1000 pieces while some Chinese are selling complete Atom boards for $45).
I've noticed that, I don't get it. So many great chips out their and you can't even get a datasheet, Broadcom for example. I once tried to use a Bluetooth chipset and they won't talk to you unless you project 500k units a year at least.
To the OP: better go for the IMX51 or IMX53. IMX23 is no longer supported. Either way you'll need to adhere to the routing guidelines. And whatever SoC you choose: use Micron memory. I've tried other brands but those just won't work reliably.
I didn't realize that. I'll look into those newer models.
Re: micron, thanks for the tip. I had spec'd a micron memory ic in my design but was not aware of the downsides of using other lesser brands.
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The IMX51 or IMX53 are pricey! A both a budget buster for me (~$20 a unit). The i.mx233 is ~$5. Freescale website shows minimum support for the i.mx233 till 2019. Thats a decent lifespan for this product, and an board redo in 5 years is ok. We'll probably replace it with something new in 2-3 years in anyway.
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Many traps for young players such as myself! I will be sure to heed all the helpful advice here. I ended up switching to a different processor (freescale i.mx233 series). It uses DDR1 only. The speed is significantly lower (133MHz or 167Mhz). Is this more forgiving or are routing rules just as strict?
No. The routing rules are quite similar, but with DDR1 you have the added complication of needing discrete termination resistors included as well - and you have to match the lengths of the traces taking both sides of these series resistors into account.
With DDR2 the termination resistors are internal to the chips, so you have to route and configure the ODT signal - but that's much simpler than having to include discrete resistors. With DDR2 you have a tree structure for the address & control bus, so you'll need to insert T points into your traces and ensure that each branch of the tree is the proper length.
Arguably DDR3 is easiest of all in terms of the PCB layout; it uses a 'fly by' topology which means the tree isn't needed, though there's more configuration and auto calibration to be done by your processor at boot time.
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Ha. Say something is impossible, and immediately it will turn out to have been done. I said:
"As things are now, it would be virtually impossible to design and market any kind of computing platform that could seriously challenge the existing status quo."
And now find this project, by Bunnie of 'Hacking the XBox' fame.
http://www.bunniestudios.com/blog/?p=2686 (http://www.bunniestudios.com/blog/?p=2686)
Building my Own Laptop
Ah ha - though I see he hasn't solved the closed design graphics engine problem:
» Vivante GC2000 OpenGL ES2.0 GPU, 200Mtri/s, 1Gpix/s (*)
Items marked with an asterisk (*) require a closed-source firmware blob, but the system is functional and bootable without the blob.
[Edit to add: found via: http://news.ycombinator.com/item?id=4925877 (http://news.ycombinator.com/item?id=4925877) ]
For his 'hacking the XBox' book, see: http://www.abebooks.com/servlet/SearchResults?sortby=17&sts=t&tn=hacking+the+xbox&x=69&y=16 (http://www.abebooks.com/servlet/SearchResults?sortby=17&sts=t&tn=hacking+the+xbox&x=69&y=16)
It's a very good read.
The XBox was Microsoft's first stab at producing a truly closed computing platform. Which was partly why they were selling it at below manufacturing cost - they needed a large user base, as a fair test of the system's security. (Plus of course, trying to break into the gaming console market.)
It was Bunnie's XBox hack that demonstrated to Microsoft that the design philosophy of the XBox security scheme was inadequate. This was why they didn't proceed to implement it in desktop PCs already - because they'd learned it would fail.
Microsoft's adapted philosophy is that for a secure hardware platform, ALL data streams between system components have to be encrypted. There should be no instances of tracks on the PCB that carry data in plaintext form. It's taking them longer to get to that objective than they expected.
The term 'trusted platform' as used by Microsoft, means 'trusted by the media copyright holders, to be secure against DRM hacking by the owner of the physical platform.' It's got nothing to do with security benefits to the owner of the PC.
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Olimex has a nice range of IMX233 based boards. Its their answer to the Raspberry Pi.
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...
As things are now, it would be virtually impossible to design and market any kind of computing platform that could seriously challenge the existing status quo. Partly for technical reasons, but mostly because the lawyers would have your balls.
The obstacles are:
- Can't use existing 3D graphics accelerator chips because nVidia etc refuse to provide opensource drivers.
- Can't substitute the 3D engines and develop open-hardware processors with high-end FPGAs because the high end chips & tools are not available to unapproved parties.
MS-Windows has become such a pile of deliberately software crippled bloatware, that it would be quite feasible to design a hardware platform and OS from scratch, using much slower CPUs and other hardware, but which still gave better user responsiveness.
It's doing decent 3D graphics independent of TPTB that is currently the killer. It's an intractable problem , and seems to be getting worse as potential ways around the monopoly get closed off.
Not sure how true that really is TBH when you look at how the mobile market is going, stuff like Adreno and PowerVR are getting quite impressive. I don't think the market is nearly as cornered as you think it might be.
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Olimex has a nice range of IMX233 based boards. Its their answer to the Raspberry Pi.
Thats how I discovered the proc. It's also used in the chumby hacker board. (also Bunnie designed).
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No. The routing rules are quite similar, but with DDR1 you have the added complication of needing discrete termination resistors included as well - and you have to match the lengths of the traces taking both sides of these series resistors into account.
With DDR2 the termination resistors are internal to the chips, so you have to route and configure the ODT signal - but that's much simpler than having to include discrete resistors. With DDR2 you have a tree structure for the address & control bus, so you'll need to insert T points into your traces and ensure that each branch of the tree is the proper length.
Arguably DDR3 is easiest of all in terms of the PCB layout; it uses a 'fly by' topology which means the tree isn't needed, though there's more configuration and auto calibration to be done by your processor at boot time.
Andy, I am starting to route my board and I have been reviewing the freescale/micron data sheets and the development board gerbers ( which I have based my design on).
Here is what I see:
Freescale does not use termination resistors in their development board. They follow the suggestions in the micron app notes but ignore termination. In the freescale hardware design guidelines they refer to a Y layout for routing to 2 ddr chips. Is this the same as "balanced T" ? I cannot find reference to "Y" routing anywhere else.
Freescale suggests keeping the tracelengths for Datalanes, strobes and masks to under 2.25cm (885 mil) but it can be longer if multiple ddr chips are used. They site an equation based on FR4 dielectric material and rise/fall time of the signal to produce this value. They then say it can be longer for multiple chips but don't explain how to calculate.
3.3 Minimizing Reflections
Keep the DRAM DATA, DQM, STROBE, and CLOCK traces short enough so that a maximum of 30%
of the edge appears on the trace. Thus, in equation form,
Trace Length ? (0.3 × Rise/Fall Time × 15 cm/ns).
The speed of a signal edge traveling from sender to receiver on widely used FR4 material is about 1/5 the
speed of light (or 15 cm/ns).
The full reflection occurs if the time for an edge travelling from sender (i.MX) to receiver (DRAM) is ?
the rise/fall time of the signal. Example:
If the rise/fall time = 0.5 ns and trace length = 7.5 cm, the receiver still sees “0 V” even though the
sender is now driving at the maximum DRAM supply voltage. Because the full edge is now on the
line, full reflection occurs.
So for this example, the signal traces should not exceed 2.25 cm (30% of 7.5 cm). This is valid for
the distance between one sender and one receiver.
Note that this example calculation is for a point-to-point connection. If more than one memory device is
connected to the bus, the rise/fall time is slower, and the trace length may be longer.
Control signals like CS, ADDRESS, RAS, CAS, and WE are not critical and can be routed without these
constraints.
3.4 Routing to Multiple DRAM Devices
In terminated systems, “daisy chain” routing is recommended because the impedance can be matched
along the whole trace. In nonterminated systems, “Y” routing is much better because it makes the trace
lengths shorter, which reduces the capacitive loading.
I analyzed all of the data lanes trace lengths in the gerber for the eval board and the results are interesting:
DQ7:1 range from 1325mil to 1457mil (+/-136mil)
DQ15:8 range from 1553 to 1635 mil (+/- 82 mil)
This spread is more than the +/-50mil micron recommends.
I'm learning quite a bit, and I feel that If I implement my design according the micron data sheet without termination I should be ok, but I am still a bit uneasy about it.
Any thoughts?
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Maybe the Freescale has internal termination resistors?
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I don't think so, I couldn't find any mention of it in the data sheet and I've seen other designs that use series termination with the i.mx233. Also from what I understand you need to pick your termination values based on layout and simulation results so having fixed value termination would not help.
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Hi Yanir.
I am very interested in what you are doing. I have been messing around with a similar design but using DDR1 memory. I haven't built anything yet but have read tonnes on the subject and still feel a little lost. This plus the cost to get a finished prototype to the test stage has seen me shelve the project until I am a little more financial.
Please keep in mind with the following text that I’m only a dumbass electrician and in the words of our venerable host, I’m probably talking out my arse.
With regards to certain manufacturers boards and the apparent disregard for signal integrity rules you would have to take into account the considerable resources at the manufacturers’ disposal.
Firstly it would be nothing for them to get a few spins of proto boards with test coupons and then carry out tests with expensive equipment to verify the boards. They can probably afford to get tight impedance controlled tolerances on the boards and have access to signal integrity software with field solver capabilities so they can layout the board and then run extensive testing before they send for them.
[conspiracy theory] Secondly it wouldn’t be surprising if the design engineers have verbal access to the chip manufactures and conversations along the lines of “Yeah the data sheets say this but we have gotten away with as much as this, if you stay within that you should be ok, I’ll email you a more realistic ibis file” [/conspiracy theory]
With reflections there are at least two things that are needed for them to occur. As you have already quoted, if the rise/fall time of a signal is less than a third of the time it takes to get to its destination you’ll create a wave on the line with sufficient amplitude to create problems.
Secondly if there is a mismatch in energy transfer somewhere along that line (vias, receiver or more specifically a change in impedance) then a reflection will occur.
If you can imagine along piece of rope and you whip one end up and down, the wave created will travel down the rope, hit the other end and bounce back. Now imagine that half way along the rope we tie a thicker rope and whip it again. When the wave reaches the heavier rope some of the energy will be absorbed by the heavier rope and the wave will continue along it although at reduced amplitude. The remaining energy will bounce back along the first bit of rope.
Going back to the first example where the one piece of rope is tied to a fixed point this is analogous to a very high impedance or open circuit. If instead of tying the rope to a fixed point we place a spring vertically with the top and bottom of it anchored and tie the string to the middle of the spring and the energy required to move the middle of the spring was equal to the energy in the wave coming down the rope, the spring would absorb that energy and the amount of reflection would be proportional to the mismatch in energy transfer other wise no reflection will occur
If you are able to match the drivers’ output impedance with the trace and the receiver then regardless of how long the trace is you shouldn’t need to add termination resistors to match impedances
With lengths being matched to each other this more to do with data arriving at the same time to avoid skew and thus data corruption.
You probably know all of this but I wanted to put it out there to see if my understanding is sound
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You probably know all of this but I wanted to put it out there to see if my understanding is sound
I don't know as much as you think. I this is my first DDR based layout and to make things "foolproof" I'm sticking very closely to the dev board design (As far as DDR is concerned).
The Freescale app note stresses layer and via matching over trace length. I'm still going to follow what micron states though.
Your impedance matching analogy is great and really helped me visualize a confusing and often poorly explained concept.
Good luck with your project, it is expensive to produce my board at proto quantities (luckily I'm not paying for it ;).
You should check out the chumby hacker board and the oilmex olixuino. They both use a 4 layer board so it's not as expensive as the recommended 6 to produce. Both projects are well documented and open source hardware.
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You don't need series termination for DDR1 when using one discrete module. (Bare chip). Micron says this themselves in one of their appnotes. Read them all.
This however is contingent upon your trace lengths staying short (1-2inches max) and no stupid routing mistakes.
For longer traces it's good to put in midpoint termination. This is because the DQ bus is bidirectional. Treat DM/DQS just like the data lines. All other signals are running at half the speed and are less critical. I have done pcbs with both setups and they worked fine, though at just 266mhz tested.
DDR2 is even better for point-to-point connection (i.e. connecting one ram chip directly to your contorller). They have on-die termination BUT this is only for data the module is driving. You will need corresponding controllable source terminations on the controller outputs. I.e.Cyclone 3/4 OCT output termination.
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You don't need series termination for DDR1 when using one discrete module. (Bare chip). Micron says this themselves in one of their appnotes. Read them all.
Thanks I'll try to find it. This design uses 2 discrete modules. Do you think that still applies?
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Andy, I am starting to route my board and I have been reviewing the freescale/micron data sheets and the development board gerbers ( which I have based my design on).
Here is what I see:
Freescale does not use termination resistors in their development board. They follow the suggestions in the micron app notes but ignore termination. In the freescale hardware design guidelines they refer to a Y layout for routing to 2 ddr chips. Is this the same as "balanced T" ? I cannot find reference to "Y" routing anywhere else.
I'd assume it's the same thing, route from the CPU to some point on the PCB, then from that point to each of the two DDR chips. Keep the lengths of the branches of the Y the same as each other.
Freescale suggests keeping the tracelengths for Datalanes, strobes and masks to under 2.25cm (885 mil) but it can be longer if multiple ddr chips are used. They site an equation based on FR4 dielectric material and rise/fall time of the signal to produce this value. They then say it can be longer for multiple chips but don't explain how to calculate.
I'm not surprised. The correct way to design a high speed interface like this is to simulate the layout with software like HyperLynx or the Cadence SI analysis software, which should fairly accurately predict the behaviour of the interface once it's been routed. The layout process is iterative: start with something that looks sensible, simulate, check timing margins and signal integrity, then modify the layout and try again. Keep going until you have a board that works.
Freescale, like other manufacturers, has no doubt done this and tried to provide some rules of thumb for other designers who don't have access to these tools - but it's not as simple as "plug these figures into this formula and you'll get something that works". They'd be oversimplifying the problem if they even tried.
I analyzed all of the data lanes trace lengths in the gerber for the eval board and the results are interesting:
DQ7:1 range from 1325mil to 1457mil (+/-136mil)
DQ15:8 range from 1553 to 1635 mil (+/- 82 mil)
This spread is more than the +/-50mil micron recommends.
I'm learning quite a bit, and I feel that If I implement my design according the micron data sheet without termination I should be ok, but I am still a bit uneasy about it.
Any thoughts?
People can get a bit hung up on length matching. With DDR2, the length matching is important in order to ensure equal delay and capacitive loading between each data bit and its associated strobe. This ensures that they all transition together at the receiver, which means there's no added clock-to-data skew that will reduce worst-case timing margins. However, if you work out the actual propagation delay involved in that 136 mil of track, I very much doubt it's significant really.
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Update, I just got my boards a few days ago and I've been testing for the past two days. I am happy to say that it boots! Memory appears to be working great (or adequately for booting at least ;) ).
Thanks for everyone's guidance. Here are some images of the DDR1 layout:
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Another interesting thing was that while getting the boards manufactured overseas (they worked) we were told by the PCB makers that there's _another_ even more strictly controlled level of secret Intel docs, that only the biggest, approved makers of Intel motherboards ever get to see.
There are other associated stories. Such as what happened to the availability of JTAG CPU emulator/debuggers for Intel processors, and the true purpose of SMM. But thats for another day.
What you're describing is what they call "red cover" access -- what you've shown here is "yellow cover". It's not really any sort of conspiracy or anything like that. As you noted, their primary goal is to sell chips, and as such, they have limited resources for doing things like design review etc. As I'm sure you're aware, doing an actual, involved design review takes considerable amounts of time and resource. Thus, they can't offer it to everyone. Clearly, they're not going to spend time for hobbyist projects, and in many cases, not for stuff that companies are running less than several thousand pieces of, because there's just not enough margin in it for them to have it make business sense.
So it follows that they don't give out sensitive documentation readily to anyone who asks for it, because there's no reason for them to take on that level of exposure for things that aren't going to go anywhere.
Also, they have to consider who they're giving it to and what their level of recourse is should it happen to leak. Basically, when you're given red cover access, you agree that should the documentation happen to leak, you are causing them an exceptional level of damage, and that they're entitled to come after you. Of course if you're a smaller company, in most cases, that doesn't add up to much.
Anyhow, that's basically the deal with this stuff.
FWIW, you can still get Intel JTAG debuggers from Wind River and American Arium.
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Nice one on the routing, but is this 4 or 6 layers? You are really missing a solid reference plane here. That is going to cause you more SI issues.
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Nice one on the routing, but is this 4 or 6 layers? You are really missing a solid reference plane here. That is going to cause you more SI issues.
Thanks!
It's a 6 layer design. I have a solid gnd plane a power plane split up for the 5 different rails. The VDDM (2.5v) rail is a solid plane under (and surrounding) the memory.
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Thanks!
It's a 6 layer design. I have a solid gnd plane a power plane split up for the 5 different rails. The VDDM (2.5v) rail is a solid plane under (and surrounding) the memory.
Good on ya. You should have zero problems with the ram (I've done much worse and had things still come in working).
I dont' recall what Vref source you used, but for only a few discrete modules a resistive divider will work fine. Two 5% 1k's is enough. They do this in commodity designs using DDR1.
Don't use a vanilla LDO because it will not properly track changes in Vddm. Purpose-designed DDR Vterm/Vref regulators have both a tracking input and regulator input.
I've used a LP2995, TI3012, and resistive divider and all worked.
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If you use a resistor divider, check the maximum Vref current that the DRAM devices can draw, and make sure your voltage output remains within spec under those conditions. I've had to use surprisingly low value, not to mention accurate, resistors for this purpose before.
Also, for the record, you should really try to ensure that your high speed DRAM signals don't cross breaks in their adjacent power or ground planes. Crossing a plane break introduces an impedance discontinuity, which can result in reflections occurring and reduced SI. Often boards with high speed DDR interfaces on them require more planes than they otherwise would for this reason.
As it's DDR1, did you not need series termination resistors in between the CPU and memory IC?
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I dont' recall what Vref source you used, but for only a few discrete modules a resistive divider will work fine. Two 5% 1k's is enough. They do this in commodity designs using DDR1.
Don't use a vanilla LDO because it will not properly track changes in Vddm. Purpose-designed DDR Vterm/Vref regulators have both a tracking input and regulator input.
I've used a LP2995, TI3012, and resistive divider and all worked.
I used a voltage divider as in the reference design. It's a 1K 1% divider with parallel 0.1uf bypass capacitors.
Thanks for the tip on the vterm/vref regulators, i'll be sure to look into those.
If you use a resistor divider, check the maximum Vref current that the DRAM devices can draw, and make sure your voltage output remains within spec under those conditions. I've had to use surprisingly low value, not to mention accurate, resistors for this purpose before.
I'll check.
Also, for the record, you should really try to ensure that your high speed DRAM signals don't cross breaks in their adjacent power or ground planes. Crossing a plane break introduces an impedance discontinuity, which can result in reflections occurring and reduced SI. Often boards with high speed DDR interfaces on them require more planes than they otherwise would for this reason.
Yes, I've read that and the VDDM plane is contiguous under most of the BGA all the way to the memory modules. The data lines do not cross any splits.
As it's DDR1, did you not need series termination resistors in between the CPU and memory IC?
The schematic for the reference design I was using did not include any so I opted to stick to it. I did review another similar design (chumby hacker board) that used series termination with a different brand of memory. I stuck with micron and the same part in the reference so I thought it was a safe bet. I also didn't have access to simulation so I wouldn't have been able to adjust the values.
Fortunately it worked.