High Speed Design Project for Highspeed Beginner

[yanir]

Hi, I'm designing a product that will utilize an ARM based processor (http://www.ti.com/product/am3352). It's a pretty powerful and inexpensive (at volume). This will be my first ARM based project and first truly highspeed project as well. I will use DDR3 memory for as well (I am basing the design off their reference design).

I've done Highspeed usb designs and RF module designs with microcontrollers running 8MHz to 12MHz. I think this should go well, and I've read up on high speed layout for such devices. Just wondering if anyone thinks this requires more experience to do properly?

[krenzo]

Just wondering if anyone thinks this requires more experience to do properly?

Maybe, but what better way to gain that experience than by trying for yourself?

Make sure to use a 4 layer board and be familiar with the following when laying out your traces:
http://en.wikipedia.org/wiki/Microstrip (for controlling the impedance of your traces)
http://www.mantaro.com/resources/impedance_calculator.htm#microstrip_impedance
http://www.mantaro.com/resources/impedance_calculator.htm#differential_microstrip2_impedance

Also, make sure you use correct termination for your differential signals:
http://www.micrel.com/_PDF/HBW/other/Micrel_HBW_Termination_Techniques.pdf

[yanir]

Thanks for the encouragement! I agree, its for work however and there is a deadline. So the pressure (self inflicted) to deliver results will be high on something new. But the challenge and learning something new is what excites me.

I'll review your links, thanks for sharing.

[jeroen74]

I believe DDR3 needs 8 layers, not 4. From the several documents I read, it's absolutely not trivial at all. Endless checklists and such. Just Google for DDR3 layout guidelines and several papers turn up.

I wish you good luck! Do you have any equipment at your disposal to debug this properly?

[yanir]

The reference design is indeed 8 layers.

This processor supports DDR1 and DDR2 so I am considering moving down if my application will run nicely on those memories. I am also looking at less hefty ARM solutions.
As far as my equipment goes I have a TEK TDS1002B 60Mhz 1GS/s scope, so an upgrade is in order. I was thinking of getting an Agilent 3000x 1.5Ghz. Would that be cutting it too close to look at DDR3 signaling?

[AndyC_772]

Actually probing DDR interfaces in a way which yields accurate, meaningful results is, frankly, so costly and involved a process that you're better off not bothering at all. You need, at an absolute minimum, a scope and an active probe with a bandwidth 10x greater than your clock frequency, and to do it properly you're in the realm of specialist adapters and solder-in headers. Budget thousands just to rent the kit for a week or two.

Most of us don't bother, though. Simulation, using a tool like HyperLynx or SigXplorer, is a better bet - though even then you'll be renting the tools or hiring someone who has them. The practical solution to DDR routing is to follow the layout guidelines which the CPU manufacturers give out, follow them to the letter, and then test your product thoroughly. There are various timings which can be programmed, so start with values which you believe should work, and then adjust them either way to find the valid window which works. You can then pick a value near the middle of that window and know that you have reasonable margins.

Laying out a board for DDR3 with just a few chips on it isn't all that complex in signal integrity terms. It only gets really bad when you start using plug-in DIMMs, and especially, more than one plug-in DIMM. If you're designing PC motherboards, for example, then you really do need expensive simulation tools.

The biggest headache can be programming up the DDR memory controller in the CPU correctly. Don't be surprised if it looks daunting; I've been hired professionally just to do this for a company before now.

[yanir]

I saw some of those those intimidating checklists mentioned.

TI addresses this in their DDR3 Doc here: http://www.ti.com/lit/an/spraav0a/spraav0a.pdf
Basically they say that although DDR3 layout is still not trivial they demonstrate a rule based approach that a designer can follow.

Andy this seems to agree with your what you say. Follow the manufacturers guidelines to a letter. I plan on using a single chip and am stripping down the reference design to remove unwanted peripherals. TI has released the BRD file which I'm reviewing. There is quite a bit going on but it doesn't look too bad. I just want to make sure my board will boot on the first spin!

Andy If I use their supplied linux/android distributions on my board will I have to program the DDR controller much?

[AndyC_772]

If you're familiar with rf design and signal integrity (length matching, controlled impedance, propagation delays and the like), then provided you follow the design rules given by the manufacturer you should be fine.

There will be things which only you know about your design: the amount of memory, the width of the address and data buses, the clock speed, the speed grade and manufacturer of the DRAM devices you're using. You'll need to either program up the DRAM controller yourself to match these, or to configure the pre-existing driver if you're using one. Hopefully the author of the DRAM driver code will document how this is done and what parameters can be configured.

[nctnico]

Designing fast memory busses comes down to keeping the data and DQ lines of a lane equal in length and try to route all the data signals on the top layer. It usually requires quite a bit of work (planning) to order the data lines and lanes so you don't need vias. Sometimes it helps to use a larger BGA packages so its easier to route the data lines away from the processor on the top layer.  The next thing are the control lines. Make these equal in length as well but they are not so sensitive because they operate at half the clock speed so using vias is not so critical. There may be length requirements / limits in the routing guidelines. You need to adhere to these closely. Forget about microstrips. There isn't enough room for those.

These kind of projects usually can be routed on a 6 layer board if you plan the design carefully. IOW think about how the PCB layout is going to look like (including the copper pours for the power planes) and which power supplies can be combined before drawing the schematic.

[TerraHertz]

Back in 2006 (?) I was involved in a design of an Intel P4 board. The specs for impedance control of many signal lines such as the high speed serial between CPU and northbridge, are extremely tight. That was where I first used a HP 54121T - the TDR capability allows measurement of PCB trace impedance and variation along the trace. It's so sensitive you can see a bump just from holding your finger _near_ the trace.

Much to our dismay, we found that all the Australian PCB manufacturers we tried were unable to achieve the manufacturing tolerance that the chips specs required. We had to have the boards made overseas, in SE Asia.
What was most disturbing was that Australian board makers didn't have the ability to qualify trace impedance directly, and most didn't seem to even understand the concept.  May have changed now.

We learned a few other interesting things about Intel CPU designs too.  The yellow books, <cough>.
A fine example of why I think corporations can never be trusted. Hey, I should tell that story, to enlighten those who seem to think such bastardry can't possibly happen. Wonder if I'd get sued?

I hope you don't have similar problems with your ARM design. If you do need to measure trace impedance, try one of these: HP N1020A TDR probe - PCB probing for 54121T. They work very nicely.

[Neilm]

One of the big issues I can see at high speed is controlled impedance. Especially if you work in a large company and the purchasing department decides to swap PCB manufacturers cos "they are all the same aren't they?"

Neil

[jeroen74]

Or when you forget to specific the thickness of the PCB if it's not the standard 1.6mm

[yanir]

Many traps for young players such as myself! I will be sure to heed all the helpful advice here. I ended up switching to a different processor (freescale i.mx233 series). It uses DDR1 only. The speed is significantly lower (133MHz or 167Mhz). Is this more forgiving or are routing rules just as strict?

[AlfBaz]

The most important aspect is flight times, clearly higher freqencies will need smaller transition times to allow the signal time to settle to a loginc high or low ( keep the eye open) but you need to see what options you have with regards to drive stength, rise and fall times. This stuff can be so anal that you have to consider the uneven distances from chip die to chip pins

[TerraHertz]

Many traps for young players such as myself! I will be sure to heed all the helpful advice here. I ended up switching to a different processor (freescale i.mx233 series). It uses DDR1 only. The speed is significantly lower (133MHz or 167Mhz). Is this more forgiving or are routing rules just as strict?

That should be much, much easier.
Speaking of traps, there are some you really wouldn't expect to encounter. Let me tell you the story of the Intel Yellow Books. Very briefly and vaguely, hoping that this won't bring down the legal harpies.

Most people would assume that a company like Intel would be all about selling chips. So you'd think the published CPU chip technical data books would contain all you'd need to produce working designs, and there definitely wouldn't be any deliberate lies or critical omissions in the data books, right?

WRONG!
It goes like this. You or your company starts work on a design. Based on published specs you choose Intel. You contact the Intel reps and ask for all available information, reference designs, etc. You get given all that, plus contacts for assisting with debugging your design. You begin the design. You hit some problems - there seem to be things just not right with the published docs. You enter detailed discussions with Intel, during which they review your design and learn all about your intended application.

At that point, IF THEY APPROVE OF WHAT YOU ARE DOING, they go "Oh hey, did we mention there are some other documents you'll need? Here they are. But they're very secret, don't tell anyone they exist. Or we will be very angry with you and you'll never get any further assistance or chip purchases from us, ever again."

That was in the period 2000-2008 (I'm being deliberately vague.)
It turns out it's flatly impossible to complete a working advanced Intel processor design without these documents. So what Intel is doing, is operating a strict gateway on who will be allowed to produce Intel CPU-based platforms.
If you're wondering why PC platform evolution seems so controlled, this is why. No disruption of the planned progression will be allowed.

Now, at this point you're probably thinking "Bullshit! Do you expect me to believe Intel would do such a thing? You damned lying conspiracy nut!"
OK then. A picture of some example yellow books. Hopefully with all identifying details, date, camera model, pixel imperfection map, etc scrubbed clean. It's an old, old pic, and I do not possess these documents and never did. I know nothing, no point asking me. Especially not names and company details. My memory is really terrible these days. But I do recall all these books had surprisingly low serial numbers. Not many ever issued, apparently.
 [Hmm. How do you make an attached image appear within the text?]

Another interesting thing was that while getting the boards manufactured overseas (they worked) we were told by the PCB makers that there's _another_ even more strictly controlled level of secret Intel docs, that only the biggest, approved makers of Intel motherboards ever get to see.


There are other associated stories. Such as what happened to the availability of JTAG CPU emulator/debuggers for Intel processors, and the true purpose of SMM. But thats for another day.

[SeanB]

Barcodes also need to be redacted...............

[TerraHertz]

Oops!
Fixed.

[SeanB]

That is how John Macafee was done..........

Depends if the Googlebot scraped it in the interim as to whether it is still visible in a cached shot..............

[ftransform]

scan that shit !


It's very underhanded of them to waste your time like that. You need to put in all that effort to have them give you the possibility of approval....
That should be illegal.

[TerraHertz]

scan that shit !

Ahem... if I had the docs... that might get lots of people in serious trouble. Much as I'd *like* to stick one up Intel. _If_ I had the docs, which of course I absolutely don't.

It's very underhanded of them to waste your time like that. You need to put in all that effort to have them give you the possibility of approval....
That should be illegal.

I totally agree. But then there are lots of things in the present world that I think should be illegal, and other illegal things that shouldn't be.  I don't have much hope of this mess getting better any time soon.

The really creepy part is when you start to look into why they do that. And connect dots with other developments, like the removal of CPU emulators from the marketplace (unless you're Intel-approved), hidden shit in the processors like the SMM activities (which you can't see without a hardware emulator, ha ha gotcha!), the ongoing efforts to make large scale FPGA development systems & chips unavailable to 'little people' (Xilinx has gone over to the Dark Side), Microsoft's self-admitted plans to 'close the box' to make DRM systems unbreakable (and lock out open source development and OSs from the PC platform) plus the near total patent-lock the 3D graphics accelerator chip makers have on graphics card development and software drivers now.

As things are now, it would be virtually impossible to design and market any kind of computing platform that could seriously challenge the existing status quo. Partly for technical reasons, but mostly because the lawyers would have your balls.
The obstacles are:
 - Can't use existing 3D graphics accelerator chips because nVidia etc refuse to provide opensource drivers.
 - Can't substitute the 3D engines and develop open-hardware processors with high-end FPGAs because the high end chips & tools are not available to unapproved parties.

MS-Windows has become such a pile of deliberately software crippled bloatware, that it would be quite feasible to design a hardware platform and OS from scratch, using much slower CPUs and other hardware, but which still gave better user responsiveness.
It's doing decent 3D graphics independent of TPTB that is currently the killer. It's an intractable problem , and seems to be getting worse as potential ways around the monopoly get closed off.

[nctnico]

I agree on the Intel story. I once had the idea of using an Intel Atom cpu in an embedded design. The sales reps came up with loads of questions and ridiculous prices ($50 per piece when buying 1000 pieces while some Chinese are selling complete Atom boards for $45).

To the OP: better go for the IMX51 or IMX53. IMX23 is no longer supported. Either way you'll need to adhere to the routing guidelines. And whatever SoC you choose: use Micron memory. I've tried other brands but those just won't work reliably.

[yanir]

I agree on the Intel story. I once had the idea of using an Intel Atom cpu in an embedded design. The sales reps came up with loads of questions and ridiculous prices ($50 per piece when buying 1000 pieces while some Chinese are selling complete Atom boards for $45).

I've noticed that, I don't get it. So many great chips out their and you can't even get a datasheet, Broadcom for example. I once tried to use a Bluetooth chipset and they won't talk to you unless you project 500k units a year at least.

To the OP: better go for the IMX51 or IMX53. IMX23 is no longer supported. Either way you'll need to adhere to the routing guidelines. And whatever SoC you choose: use Micron memory. I've tried other brands but those just won't work reliably.

I didn't realize that. I'll look into those newer models.

Re: micron, thanks for the tip. I had spec'd a micron memory ic in my design but was not aware of the downsides of using other lesser brands.

[yanir]

The IMX51 or IMX53 are pricey! A both a budget buster for me (~$20 a unit). The i.mx233 is ~$5. Freescale website shows minimum support for the i.mx233 till 2019.  Thats a decent lifespan for this product, and an board redo in 5 years is ok. We'll probably replace it with something new in 2-3 years in anyway.

[AndyC_772]

Many traps for young players such as myself! I will be sure to heed all the helpful advice here. I ended up switching to a different processor (freescale i.mx233 series). It uses DDR1 only. The speed is significantly lower (133MHz or 167Mhz). Is this more forgiving or are routing rules just as strict?

No. The routing rules are quite similar, but with DDR1 you have the added complication of needing discrete termination resistors included as well - and you have to match the lengths of the traces taking both sides of these series resistors into account.

With DDR2 the termination resistors are internal to the chips, so you have to route and configure the ODT signal - but that's much simpler than having to include discrete resistors. With DDR2 you have a tree structure for the address & control bus, so you'll need to insert T points into your traces and ensure that each branch of the tree is the proper length.

Arguably DDR3 is easiest of all in terms of the PCB layout; it uses a 'fly by' topology which means the tree isn't needed, though there's more configuration and auto calibration to be done by your processor at boot time.

[TerraHertz]

Ha. Say something is impossible, and immediately it will turn out to have been done. I said:
"As things are now, it would be virtually impossible to design and market any kind of computing platform that could seriously challenge the existing status quo."

And now find this project, by Bunnie of 'Hacking the XBox' fame.
  http://www.bunniestudios.com/blog/?p=2686
  Building my Own Laptop

Ah ha - though I see he hasn't solved the closed design graphics engine problem:

  » Vivante GC2000 OpenGL ES2.0 GPU, 200Mtri/s, 1Gpix/s (*)
  Items marked with an asterisk (*) require a closed-source firmware blob, but the system is functional and bootable without the blob.

[Edit to add: found via: http://news.ycombinator.com/item?id=4925877 ]

For his 'hacking the XBox' book, see:   http://www.abebooks.com/servlet/SearchResults?sortby=17&sts=t&tn=hacking+the+xbox&x=69&y=16
It's a very good read.

The XBox was Microsoft's first stab at producing a truly closed computing platform. Which was partly why they were selling it at below manufacturing cost - they needed a large user base, as a fair test of the system's security. (Plus of course, trying to break into the gaming console market.)
It was Bunnie's XBox hack that demonstrated to Microsoft that the design philosophy of the XBox security scheme was inadequate. This was why they didn't proceed to implement it in desktop PCs already - because they'd learned it would fail.
Microsoft's adapted philosophy is that for a secure hardware platform, ALL data streams between system components have to be encrypted. There should be no instances of tracks on the PCB that carry data in plaintext form. It's taking them longer to get to that objective than they expected.

The term 'trusted platform' as used by Microsoft, means 'trusted by the media copyright holders, to be secure against DRM hacking by the owner of the physical platform.' It's got nothing to do with security benefits to the owner of the PC.