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| High Voltage Bench Power Supply Design |
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| Wolfgang:
--- Quote from: cur8xgo on June 25, 2019, 02:56:39 am ---This makes me wonder... Is there: -a reliable, robust method to parallel 100 TO247 or TO220 fets -a fet which is cheap that could be paralleled using that method, to essentially create some giant combined fet that could handle linear mode dissipating 5KW or more no problem into a water cooled heatsink or what not? --- End quote --- lets see ... - even the linear rated IXYS FETs have a max. dissipation of ca. 100W per chip in TO247 case in linear mode - that makes 50 FETs a 10$ each, if your need 5kW,. - and, you have to make sure that they are equally loaded. Meaning the balancing resistor drop is several time the variation in threshold voltage. - Then, your total gate input capacitance is in the range of a microfarad, and it must be driven from a really low impedance. Plan B: Make 5 driver modules a 10Fets, each with a separate driver. You could stack this scheme until you have the current capability you need. Another thing you could consider at 5kW is a tube. The circuit will be a lot simpler, the mechanics not so much. have fun, play safe Wolfgang - |
| duak:
I've posted a reply in this thread earlier on. To re-iterate, MOSFETs have a problem called "electro-thermal instability" when used as pass transistors when they have to support a high drain to source voltage at low currents. (see 1st attachment). The other papers talk about it in more detail. Basically, MOSFETs have multiple cells and each one has a slightly different threshold and transfer function. This means that they don't share the current equally and then localized hot spots develop. At some point, a cell will fail, short out and the device is pretty much useless. What can one do about it? - IXYS linear FETs are better, but they still exhibit the problem. I found that out when testing a high voltage electronic load. - older, high voltage FETs are better than new ones that are optimized for switching. - the FQA8N90C-F109 shouldn't be too bad because of their 900 V Vds rating. However, it uses a newer cell design so it likely was optimized for switching. - use larger source resistors to better distribute the current among the FETs. I would say something that develops 5-10 V at full current. - use a foldback current limiter to reduce output current at lower output voltages. This can be done with a high valued resistor from the drains of the FETs to the base of current limiter transistor. It will need a resistor between the base of the transistor and the current sense resistor. However, the extra current from this resistor may increase the minimum output voltage slightly because it is bypassing current around the pass transistors. Food for thought: I've been thinking that dithering the drive to the FETs might be a solution. This is where a high frequency signal is applied to a system that has a granular response and the output is filtered to remove extraneous noise. An example of this is the 50 - 100 KHz bias used in analog magnetic recording to reduce distortion. |
| Wolfgang:
Hi, I personally have never seen an IXYS MOSFET fail in linear mode. I run them at max. 70% or their max. dissipation spec in linear mode, and with 80% of rated voltage, so no extraordinary precautions. Dithering does not help much, if you do that you could resort to a switching regulator right from a start. The ripple removal effort will be similar, and then normal switching MOSFETs could do the job. regards Wolfgang |
| H713:
Where did the 5kW number come from? 500v * .5A is a maximum of 250W. If that .5A got reduced to 350mA I could live with that so long as I have a reasonable safety margin. If I could find a FET that could reliably handle 600V at 200mA that would be fine as there will be 4 in parallel. The other thing I can try is putting the FETs in series rather than in parallel, though I don't expect that the improvement will be drastic. |
| MagicSmoker:
--- Quote from: H713 on July 08, 2019, 06:04:52 pm ---If I could find a FET that could reliably handle 600V at 200mA that would be fine as there will be 4 in parallel. The other thing I can try is putting the FETs in series rather than in parallel, though I don't expect that the improvement will be drastic. --- End quote --- Parallel operation of MOSFETs in linear mode is perilous business because their gate threshold voltages have a negative tempco and they are also prone to vicious oscillations. I would expect to derate to no more than 25W Pd for a TO-247 package and they absolutely must be on a common heatsink for good thermal coupling. So, plan on requiring 8-12 in parallel, not 4. If you can get the Vds drop down to 100V or less via series wiring, however, each MOSFET will be able to handle the full 500mA so only 4-6 should be necessary. The MOSFETs are much less prone to oscillation when in series and the negative threshold voltage tempco is also not a problem (just results in unequal voltage sharing). It's a bit trickier to wrap your head around how a series cascade works, and there will be a larger minimum dropout voltage, but that is usually not a problem in a HV regulated power supply. |
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