High voltage PCB clearance

[Digibin]

I have a question about achieving reasonable clearance between high voltage traces on a PCB. I've designed an off-line push-pull converter and have started to layout a board to build and test it. I want to maintain a clearance of 3mm minimum between the high voltage traces. This is fine when routing the traces, but the pads for some of the parts I'm using don't achieve the 3mm clearance. For example this MOSFET: Infineon IPA90R500C3.

The pins are standard 0.1" pitch. So my clearance rule of 3mm is immediately violated. The part is clearly designed for high voltage applications. My 3mm rule is just based on some googling and some clearance calculators, it seems reasonable to me. So why does a part designed for high voltage have a pin pitch that renders it unusable under many safety directives?

The pins are 2.54mm pitch and 0.85mm max wide. So the smallest you could make your pad hole is about 1mm diameter. The pad around the hole is then going to be about 2mm diameter. This only leaves you with just over half a mm clearance between the two pads.

Even if my clearance of 3mm is overkill, half a mm seems way too small. What's the deal here?

[Benta]

First you need to tell us what you mean by "high voltage". For some engineers, this starts beyond 10 kV...

I suspect you are talking 120 VAC or 230 VAC input.

I can't say anything about 120 VAC.

For 230 VAC systems, the phase-to-neutral creepage distance on traces directly connected to the mains is 3 mm.
Input-output (phase or neutral to something the user can touch) creepage distance is 8 mm. This can be lower if the equipment has protective earth.

For the phase-to-neutral, the operative phrase is "directly connected to the mains". This means, that if you insert a fuse on your PCB, the traces downstream from here do not need to fulfil that criteria. But generally, the 3 mm distance is good design practice.

Hope this helps.

Benta.

[Digibin]

Sorry yes 230VAC UK mains, through an active PFC circuit producing 400VDC.

The question is less about the appropriate clearance distance I should design for and more about how to actually achieve that distance when parts like the MOSFET I linked to have a pin pitch which render it impossible.

[Benta]

The creepage distance on TO-220 where the pins meet the epoxy is around 1 mm, on your device more like 1.5 mm, so that's what I'd aim for. I would not go below 1 mm.

[Gyro]

Yes, it is a compromise. Creepage distance across an epoxy package tends to be safer (as in insulation being more defined) than on a PCB, with no-clean flux residues etc. It's fairly common in SMPSs to pre-form the leads (center lead brought forward) in order to improve spacing. Many integrated switcher ICs come pre-formed in that way. Yes, you should strive for 3mm (at least in the early stages of the primary section) but at some point you have to compromise to the most you can achieve.

Don't forget 8mm clearance primary to secondary / case / ground. It's best to maintain Class II clearances, even in a grounded chassis situation.

[Digibin]

Okay so since this is a one-off board I could easily preform the centre leg of the MOSFET. But with a voltage rating of 900V surely the TO-220 package is just not suitable? I don't see how this part could make its way into certified devices.

So my next question then following this is how to setup the PCB design rules to account for this. I'm using Altium. I've set the clearance to 3mm on all high voltage nets. I've set this to something smaller for clearance between component pads. So the pitch of the pins doesn't violate the rules. However as soon as you place a trace on the pads, it's now a trace-to-trace clearance and a violation occurs. So I'm just curious how one should setup the design rules in a scenario like this.

[max_torque]

It really depends on the pollution class for which you are designing.  For a new, clean pcb, at sea level, in a low humidity and clean environment 1mm is a large distance.  It would take >5Kv to jump across that gap.

But an old, "dirty" pcb (flux residue etc) at altitude, with high humidity and in a dusty environment is a VERY different proposition indeed!


And with all things MOSFET, the maximum ratings are really just a guide, typically you'd only use between half and two thirds of the ultimate capability for your "DC" values, leaving room for dynamics overshoots etc.  So, you wouldn't actually use a 900V mosfet on a 900V dc link....

[Benta]

Frankly, when doing stuff like this I switch off the design rules and switch on common sense. Disclaimer: I've never worked with Altium, so I don't know the limitations.

It's normally not a circuit with hundreds of nets and you should remind yourself it's called PCB Artwork.

In tight spots, a workaround is making a slot in the PCB, this changes the game from creep distance to air gap.
It's often done under optocouplers to achieve the 8 mm input-output distance.

[T3sl4co1l]

Why'd you choose push-pull at 400V DC link?

(Do you mean totem pole or half-bridge?)

Tim