High-Z wideband buffer amp for 50 ohm CRO inputs

[GK]

I'm not going to bootstrap Vds to save maybe one pF of input capacitance when I can just select one of many parts that will give me one pF less input capacitance to start with.

[joeqsmith]

Attempted to send you a PM but "User 'GK' has blocked your personal message."

I'm curious what limitations you have.  Bandwidth, or possibly blocked due to the music?    Info may help me with future videos.

Thanks

"I can't watch the vid (internet connection limitations), but I think the op-amp approach is practical if you can live with a high ratio of fixed attenuation at the input."

[joeqsmith]

Maybe this is of interest:

http://www.amazon.com/High-Z-Spectrum-Analyzer-Amplifier-FETAMP1/dp/B00MEVDX70

Some of the new amps are not too bad. 

[GK]

Hmm... I've put JFET-input op-amp ADA4817-1 on my next order.

[joeqsmith]

Video was an OPA6xx on one of their eval boards.   Be interesting to see what you come up with.

Hmm... I've put JFET-input op-amp ADA4817-1 on my next order.

[GK]

Be interesting to see what you come up with.

The OPA657 looks nice, but doesn't have the slew-rate and +2 gain bandwidth required. The ADA4817-1 however looks to be the bee's knees as far as FET-input op-amps go in terms of bandwidth and slew rate. On +/-5V supplies the ADA has a specified slew rate of 870 V/us, but that is with a 4V input step which will massively overload the input stage and deliver the full tail current to the internal compensation capacitance for the longest duration of time. For a gain of +2 set with a pair of 200 ohm feedback resistors, it appears from the small and large signal response plots provided in the datasheet that the effective slew rate for sinusoidal signals is in the order of 600-650 V/us and the -3dB bandwidth 400 MHz with no HF peaking. That will support an output sine of 0.4V peak at 250 MHz.

That is more than adequate performance so it looks like there is no point in pursuing the discrete implementation. Sad, as I was quite enamored with my JFET buffer and auto-zeroing scheme, lol.

The evolved circuit, now in its third iteration, appears below. I've shifted the AC/DC coupling relay and cap to after the input attenuator; I decided that I didn't want the additional path inductance between the probe and the shunt termination capacitance. From experience I'm still a bit paranoid about terminating the input of such a high speed op-amp to such a high source impedance. The 1.8pF cap and the 100R resistor in the schematic will be put right at the non-inverting input pin. 1.8pF at 400MHz = 220 ohms, which should nicely keep the input terminated into a low Z at frequencies that could otherwise prove troublesome for pick-up and regeneration. The 100R will neuter any series resonant peaking between the input C and the net trace/component inductance of the loop closed by the shunt termination capacitance over at the input attenuator. Well that's the theory anyway. Proof will come in solder. I'm starting the board layout for a prototype channel now. 
 




   

[joeqsmith]

I was using a 53 that uses the built-in network.   Was looking to get 100MHz with a fixed gain and 60Vp-p.  Video compared results of coax vs a 10X w/driver from DC to 400 or so MHz.    4V step for the 53 is 2675V/us with a gain of 2V/V and 100 ohm load.   

The OPA657 looks nice, but doesn't have the slew-rate and +2 gain bandwidth required. The ADA4817-1 however looks to be the bee's knees as far as FET-input op-amps go in terms of bandwidth and slew rate. On +/-5V supplies the ADA has a specified slew rate of 870 V/us, but that is with a 4V input step which will massively overload the input stage and deliver the full tail current to the internal compensation capacitance for the longest duration of time. For a gain of +2 set with a pair of 200 ohm feedback resistors, it appears from the small and large signal response plots provided in the datasheet that the effective slew rate for sinusoidal signals is in the order of 600-650 V/us and the -3dB bandwidth 400 MHz with no HF peaking. That will support an output sine of 0.4V peak at 250 MHz.

That is more than adequate performance so it looks like there is no point in pursuing the discrete implementation. Sad, as I was quite enamored with my JFET buffer and auto-zeroing scheme, lol.

The evolved circuit, now in its third iteration, appears below. I've shifted the AC/DC coupling relay and cap to after the input attenuator; I decided that I didn't want the additional path inductance between the probe and the shunt termination capacitance. From experience I'm still a bit paranoid about terminating the input of such a high speed op-amp to such a high source impedance. The 1.8pF cap and the 100R resistor in the schematic will be put right at the non-inverting input pin. 1.8pF at 400MHz = 220 ohms, which should nicely keep the input terminated into a low Z at frequencies that could otherwise prove troublesome for pick-up and regeneration. The 100R will neuter any series resonant peaking between the input C and the net trace/component inductance of the loop closed by the shunt termination capacitance over at the input attenuator. Well that's the theory anyway. Proof will come in solder. I'm starting the board layout for a prototype channel now. 

[GK]

Oh, I somehow missed that one. It didn't come up for me in the TI site parametric search.

[GK]

Hmm.... added a SOT23-5 OPA653 to my next outgoing order list. The small signal bandwidth is in excess of my requirements, but the much better large signal bandwidth would be desirable. I'd do two prototype/test layouts; one for the OPA and one for the ADA.
 

[joeqsmith]

Maybe you could roll all three.   Hate to think I spoiled all your fun. 

Hmm.... added a SOT23-5 OPA653 to my next outgoing order list. The small signal bandwidth is in excess of my requirements, but the much better large signal bandwidth would be desirable. I'd do two prototype/test layouts; one for the OPA and one for the ADA.
 

[GK]

That would be nice if there were 48 hours in a day, but I have too many projects on the go and the goal here is just to get a 4-ch probe buffer amp completed. I'll start with the OPA653 and if that works out that is what I'll stick with. 4 channels will be layed out on a single PCB along with a PCB-mount torodial mains transformer and associated power supply. The whole thing will be housed in a die-cast aluminum enclosure.

I wish the '53 datasheet contained a bit of discussion on the thermal characteristics of the SOT-23 package. The only thermal spec. given is a figure of 105 degrees C per W for the thermal resistance junction to ambient. Although that is a useless spec. for a tiny SM device that will dissipate most of its power via the copper traces emanating from its pins if the manufacturers test jig/PCB is unknown it generally is a useful figure for comparison between different devices. 105 deg.C/W seems a remarkably low figure. Having just perused several data sheets for other op-amps in the 5-lead SOT-23 package, I get figures ranging 210 to 280 deg.C/W. I wonder what would make the '53s die/encapsulation such a standout performer in this regard?

The '53 has a quiescent current of 32mA, which is 320mW on +/-5V rails just sitting there doing nothing. For a SOT-23 package with a more ordinary/typical specified junction-ambient thermal resistance, that's getting pretty damn toasty.

Given such a high quiescent current I wonder if the super slew rate spec was achieved solely by running really hot class A bias on the gain stages that drive the compensation capacitance, or if to some degree a "current on demand" architecture is used, which would see the no-load quiescent current and internal dissipation rise further when driven with a signal that exercises the devices full power bandwidth. 

I'm going to torture test the first one I get soldered. In any case it's a given that a decent amount of top-layer copper will need to terminate to the power supply pins and the output pin to get the heat out of the SOT-23 package.


     
     

[GK]

Unfortunately my parts order didn't turn up before the weekend, so I won't have any bench tests to report until next weekend. Here is the layout section for a single channel. Might get the board etched tomorrow.

[joeqsmith]

Looks like your making some good progress with it.    Assuming you ditched the micro.  What's your plan for controlling the relays? 

[Mechatrommer]

so you've ditched out all the mid section discrete jfet input section from the original design and went to raw jfet opamp? thats interesting , i remember deleting my suggestion due to maybe there are specialty in using discrete jfet for a oscilloscope like every brands did. whats more interesting you also ditched out the null offset circuitry, instead of going from mcu to full analog, you go for none at all. i wonder what will be the end output dc offset...

[GK]

Looks like your making some good progress with it.    Assuming you ditched the micro.  What's your plan for controlling the relays?

I have a bag of miniature PCB-mount toggle switches. These will supported on a separate PCB mounted directly behind the lid of the diecast aluminum box that this whole thing is going to be enclosed in. This switch board will connect to the analogue board via a short length of ribbon cable.

I've done some revisions to the 4-ch PCB layout, re-arranging the compensation and termination capacitors of the passive input stage to reduce the length of the inductive tracks between them. I've used 1206 for ease of assembly (home-etched PCB) but if I wanted to go a level better it would be 0603 with components on both sides of the board and lots more (smaller) vias.

[GK]

i wonder what will be the end output dc offset...

OPA653 typical (25 deg C) input bias current and input offset voltage are 10pA and 1mV respectively.

[GK]

One last revision. I decided to add an output offset voltage trim. The PCB layout is done; I'll etch it this evening and load it next weekend. The signal outputs will be BNC panel-mount jacks connected to the PCB via short lengths of coax.

[tggzzz]

That silly squared background on your schematic obscures the content. How? It makes it unnecessarily difficult to see where connections aren't. And that rather negates the whole purpose of a schematic!

While it maybe helpful to you when drawing the schematic, could you please consider your readers by turning it off when publisihing your schematic.

[tautech]

That silly squared background on your schematic obscures the content. How? It makes it unnecessarily difficult to see where connections aren't. And that rather negates the whole purpose of a schematic!

While it maybe helpful to you when drawing the schematic, could you please consider your readers by turning it off when publisihing your schematic.

It's just the visible grid, quite invisible if you are used to it. 
What's more important when laying out schematics and PCB's is the snap grid which may be set the same as the visible grid and in PCB layout packages should be selectable or better still totally user definable.
Everyone has their own preferences. 

[joeqsmith]

Looks like you have given up on the Analog Devices part now and going for a final solution with the TI.   

[GK]

Yes, as I wrote in reply #35.

[joeqsmith]

I feel I need to ask to make sure I get the latest info.      What's you plans for evaluating its performance?   Video in the works?

Would have liked to see if your discrete design would have less noise.

Yes, as I wrote in reply #35.

[Mechatrommer]

What's you plans for evaluating its performance?

it only can be evaluated when the proper pcb is ready and populated, this is a costy and wasty business, from a hobbiests POV. and where experience dominates the theory textbooks.

[Yansi]

Maybe a silly idea, but what about the "classic" solution, using the discrete buffer for AC highspeed signal + DC servo for the rest? (Instead of using veeeeery very fast opamps with fbomb cost level) 

If already mentioned, sorry, I haven't read everything carefully. But it is  definitely interesting topic, as I am currently in the process of designing the same thing (1M to ~50R buffer), but only for <100MHz BW (building it just for my analog circuit curiosity and experimenting) 

[GK]

Would have liked to see if your discrete design would have less noise.

The majority of noise comes from the op-amps and the single OPA653 circuit is less noisy than the two op-amp circuit I followed the discrete JFET buffer with.

Quick analysis:

On the x1 attenuator setting (20dB attenuator switched out). The input is terminated in 1M || 18pF. Consider that the input is disconnected/floating.

1M corners with 18pF at 8842Hz. This is a single pole, low-pass response. A single pole LPF has an equivalent noise bandwidth of pi/2*fo, so:

pi/2 * 8842 = 13890 Hz.

1M generates 129nV/rt Hz of thermal noise at room temperature. The OPA653 has 1.8fA/rtHz input current noise:

1M * 1.8fA = 1.8nV.

Additionally, as noise sources sum as the square root of the sum of the squares, the current noise contribution is totally negligible and can be neglected.

So, the net rms noise contribution from the passive input network is therefore:

SQRT(13890Hz) * 129nV = 15.2uV rms.

This drops even lower when the 20dB attenuator is switched in as the 10:1 attenuator an impedance reduction as presented to the op-amp input.

It's often blithely stated that the noise performance of a CRO/DSO with 1M inputs is limited by the impedance of said input. Until someone can design a 1M input with next to no shunt input capacitance this will remain total BS. It's the wideband amplifiers/ADCs that are the noise performance barrier.

The OPA653 is speced at 6.1nV. Its 500MHz (lets just assume first order for a close enough simplification) frequency response returns a noise bandwidth of:

500MHz * pi/2 = 785MHz, so...

SQRT(785M) * 6.1nV = 171uVrms

Lets sum this with the worst case (15.2uV) noise contributed by the passive input stage:

SQRT((15.2*15.2)+(171*171)) = 171.67uV.

So the 1M input network (worse case) contributes:

log20*(171.67/171)

= 0.034dB to the total rms noise!


171.67uV of rms noise in a 500MHz bandwidth is pretty negligible when viewed on an oscilloscope with 10mV/div vertical sensitivity, so this buffer amplifier won't be a performance barrier in terms of noise performance in almost all cases of use.


NOTE: for simplification I've neglected in the above the <100kHz 1/f noise of the OPA653, but if you do the sums you'll find the contribution to the total rms noise quite negligible.