Author Topic: 74 Series Logic Design: Equation optimiser?  (Read 741 times)

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Offline NivagSwerdnaTopic starter

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74 Series Logic Design: Equation optimiser?
« on: August 03, 2020, 08:26:47 am »
I know I am about 50 years out of date but...

Given a set of Logic Inputs and a set of boolean equations (AND, OR, NOT, XOR) is there a method to optimise for a set of 74 series ICs to realise the equations?

e.g. Given a set of equations with lots of ORs the actual best solution might be to use Quad NANDs ?

Or did designers just use pen, paper and deMorgans?
 

Offline Ian.M

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Re: 74 Series Logic Design: Equation optimiser?
« Reply #1 on: August 03, 2020, 08:53:33 am »
If you've got a windows PC, you may find Logic Friday useful.  Its a GUI frontend for the Espresso logic minimizer  The original website's gone to domain parking, but it can still be accessed, including downloading the installer, [here] at the Internet Archive.

However that wont spot for you when it would be preferable to use MSI logic chips like a magnitude comparator, or 74xx138 and '238 three to eight line decoders, which can pick out a single condition from any four input signals, or any condition with at least one '0' input from five signals or any with two '0'and one '1' from six signals.
 
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Offline NivagSwerdnaTopic starter

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Re: 74 Series Logic Design: Equation optimiser?
« Reply #2 on: August 03, 2020, 09:35:12 am »
Thanks Ian.M

I couldn't get your link to work but I managed to find it here https://logic-friday.software.informer.com/download/

And it did the job instantly!

 

Online Alex Eisenhut

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Re: 74 Series Logic Design: Equation optimiser?
« Reply #3 on: August 03, 2020, 10:58:04 am »
Hmm, I'm also out of date but for small systems isn't that

https://en.wikipedia.org/wiki/Karnaugh_map
Hoarder of 8-bit Commodore relics and 1960s Tektronix 500-series stuff. Unconventional interior decorator.
 

Offline NivagSwerdnaTopic starter

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Re: 74 Series Logic Design: Equation optimiser?
« Reply #4 on: August 03, 2020, 11:06:23 am »
... yes and minterms and maxterms and all that.  It's nice to have some tools though!  ;)
 

Offline tggzzz

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Re: 74 Series Logic Design: Equation optimiser?
« Reply #5 on: August 03, 2020, 11:20:05 am »
Never forget "bridging terms" in K-maps. Without them you have dynamic hazards, which can be a killer in some circuits.

Be aware that a simulator may or may not reveal the hazard, depending on whether is models "inertial delays" or "transport delays".

Forgetting about those almost allowed me to submit a synchronous IC design that would have failed (3 months turnaround, years salary NRE).
Remembering them allowed me to diagnose why a large chunk of metal moved uncontrollably until the power was cut. That one wasn't my design :)
There are lies, damned lies, statistics - and ADC/DAC specs.
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Online Alex Eisenhut

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Re: 74 Series Logic Design: Equation optimiser?
« Reply #6 on: August 03, 2020, 05:26:50 pm »
... yes and minterms and maxterms and all that.  It's nice to have some tools though!  ;)

For sure. Brings back good memories, I was pretty good at this in school... um many years ago.

It also helped me understand how the tool I was using at the time at work did its job. It made me overconfident at work, I was asked if I could take a discrete logic design and fit it into a PAL or GAL or whatever it was back then, a 22V10 or something.

Before even looking at the details I said sure! and took it on.

Turns out it was some kind of ad-hoc sequencer made with a handful of flip flops and combinatorial logic driving the sequence.

I was in trouble but somehow managed to get it to work through sheer persistence and lots of trial and error.  :-/O

On the strength of that success I was given a XC9572 design! I still have that board around somewhere. Late 1990s. Good times. ^-^
Hoarder of 8-bit Commodore relics and 1960s Tektronix 500-series stuff. Unconventional interior decorator.
 
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