It's fine, you have the overlap.
It'll still work if they weren't overlapped -- probably -- but how well, isn't something you can know for sure from these datasheet values, and relying on that active word "probably", would be a poor idea for design purposes. For example, the 70% threshold of 74HC CMOS (3.5V) exceeds the best-case 3.3V supply, so would not be a reliable combination. It would likely work in a typical case (I believe HC thresholds are usually close to 40-50%?) -- but you can't guarantee that for every unit produced, under all operating conditions.
I would be shocked if the ESP's output isn't very damn close to 3.3V even with a modest (some kohms?) pull-up/down on it, it's just that they rate it at whatever current they do, and the worst case margin in that condition is quite pessimistic. Probably, anyway; I didn't look at the datasheet.
But do be mindful of anything that will reduce that margin. Noise, indeed; which especially means CM noise around a power converter -- use solid ground plane between them. Variation in supply voltage; maybe you want to adjust the 3.3V regulator upward a little to increase that margin (what's the ESP rated for, 3.6V max? 3.4-3.5V would be safe enough). Or shut down the HIP preemptively if the 3.3V supply starts to drop -- add a power monitor chip perhaps. Which is a good idea anywhere you're doing something fairly mission-critical, like pulsing an inverter with a MCU, anyway. Not to mention a keep-alive or watchdog timer, which might include external (analog) circuitry to lock out the inverter, in hardware, in case the MCU stops responding, or responds erroneously. For that matter, if you're adding external logic, you might as well get the level shift for free (use 74HCT at 5V?) and avoid the problem entirely. So there are many options to choose, as far as prudence goes.
Tim