Power switching in low-power designs: high-side or low-side?

[philpem]

I'm working on a design which runs from a DC supply, but when that supply is interrupted it switches to a supercapacitor and begins taking A/D samples from several sensors at fairly long intervals (up to a second between samples). The goal is to sample for as long as possible, or until the EEPROM is full. On the next power cycle, the EEPROM data is analysed and "magic hand-wavy wibbly-wobbly timey-wimey stuff" happens

As the sensors and associated amplifiers (an instrumentation amplifier mated to an active filter built from a dual opamp) consume rather a lot of power, I'd like to keep them powered down until they're needed (the CPU already halts and uses timer interrupts to wake up to take a sample).

In my own designs, I add a FET switch the VCC line to any peripherals I may need to switch off. This design does the same, but switches the op-amp's ground path instead.
The reasons for the low-side switching scheme have been lost to the sands of time, other than "we've done it like that on other designs and it's always worked fine".

Is there any particular advantage or disadvantage to switching the ground path (low-side switching) instead of the VCC path (high-side switching)?

I was thinking there was a risk of creating a leakage path from VCC to GND through the amplifier output (thus wasting power), but I'm not sure if that's a plausible explaination.

Cheers,
Phil.

[lgbeno]

Low side switches are typically used because they are easier to deal with from logic level devices.  Meaning that with a gnd referenced micro, you drive 3.3v to the gate of a low side NMOS and achieve switching.  If doing highside, you would need to use PMOS which are typically more expensive for the equivalent Rdson and have higher gate capacitance.  Also you would need to drive the PMOS gate all the way up to VCC to turn it off so if VCC is say 5v and you have a 3.3v micro then level shifting would be required to drive that PMOS.


So to answer your question, low side switching is cheaper and easier but the con is that you may have shifts in you ground references if different parts of the circuit that are switched with different fets.  Also issues with wiring and chassis grounding come into play for large systems.

[T3sl4co1l]

Consider what happens to the input and output voltages when the supply (either one) is cut to a subcircuit.  Almost all ICs have input and output protection diodes.  Few have "disconnected when unpowered" pins.  More often, "micropower" devices come with enable pins which allow the chip to remain supplied (and thus the input/output voltage range stays the same), while disabling internal bias (resulting in microamperes of current draw).

If your measurements are between seconds, then you must not need much bandwidth.  Surely you can find precision micropower op-amps for the task?

Also, you can't disable an active filter.  At best, you can freeze it, and it will retain the last state, but more likely it will end up reset to zero.  So your settling time is going to be terrible, especially if the bandwidth is anywhere near what your sample rate suggests (i.e., <1Hz).

Overall, this sounds like a project that hasn't had any coherent understanding or attempt at saving power -- if your amps consume "rather a lot", it probably doesn't matter one iota whether the CPU is running balls-out or not, does it?

So, simplify the problem, make an analogy: something easier to work with.  What if you were doing it completely low level with state-of-the-art '70s tech?  You could have:
- Analog input stages
- Power/bias enables, analog switches, S&H, etc. as needed
- ADC (of whatever type -- D-S, flash, SAR..), parallel out
- SRAM -- CMOS, with battery backup (microamperes -- only draws significant current during pin / state changes)
- Digital logic -- address counter, clock and divider, etc. (also CMOS)
- Maybe a bus arbitration thing to allow outside access (e.g. reading it out via parallel port) from a powered device, as well as other assorted logic for housekeeping (address reset, buffer overflow stop, battery "low" indication or logging, etc.)

With a little more work, a serial ADC (much more common these days) and serial EEPROM could be used, plus whatever interface method (e.g. RS232 ASCII terminal?); at this point, you'd be looking at a low power FPGA to handle all the sequential logic, or even some software.

It's pretty clear that, however you cut the digital stuff (all in MSI hardware, or embedded, or bit-banging it all in software), it's not a threat, at all.

If you can better define the analog requirements (voltage or current, and how much of each, precision, bandwidth, sample rate, noise, etc.), we can offer better comments / example scenarios.

Tim

[philpem]

Overall, this sounds like a project that hasn't had any coherent understanding or attempt at saving power -- if your amps consume "rather a lot", it probably doesn't matter one iota whether the CPU is running balls-out or not, does it?

It's not the amplifiers which consume the power -- it's the sensors. They're resistive bridge sensors and consume a few milliamps -- more than the CPU.

If you can better define the analog requirements (voltage or current, and how much of each, precision, bandwidth, sample rate, noise, etc.), we can offer better comments / example scenarios.

The signal being tracked can take between two seconds and two minutes to get from 100% to 0%, depending on the physical apparatus the device is connected to. The goal is to get 1000 samples during that time, which equates to a sample rate of between 8Hz and 500Hz.

Resolution? The 12 bits provided by the A/D (it's an STM32 chip) is fine.

Noise? Mostly 50Hz coming in the signal lines. There's a bit of hash from the switching regulator, but an LC filter should nicely deal with that.

[suicidaleggroll]

I use both high and low side switching quite often, it really depends on what you're cutting power to and how it's wired (what else is it attached to?  What will the line states be?  What is the other device doing while power to the device in question is cut?)

As lgbeno said, low side switching is generally cheaper and easier to implement, provided your circuit will work correctly with low side switching.  High side switching is easy if the voltage you're switching is the same or lower than your control voltage, otherwise you probably need to use an Nmos to switch the Pmos gate so you can "insulate" your controller from the higher switched voltage.

[T3sl4co1l]

Ah, excellent.  Then, if you turn on VREF to the bridge for, say, a few microseconds at a time, and sample only during that time, you have very little chance of interference from any source of noise -- uncorrelated noise then goes as 1/sqrt(N), so at worst, you could increase your sample rate a little (relative to the continuous, fully filtered and polished case) to compensate.

You'd probably want to use a high side switch, but if VREF is within the supply rails, it can be an analog switch device.  Don't forget to also sample VREF from *after* the switch, not before, so you don't miss the switch's voltage drop.

Tim

[philpem]

I use both high and low side switching quite often, it really depends on what you're cutting power to and how it's wired (what else is it attached to?  What will the line states be?  What is the other device doing while power to the device in question is cut?)

It's literally just a sensor (think Wheatstone bridge), an instrumentation amplifier to remove the offset and amplify the signal, then a two-pole Bessel-response Sallen-Key filter to act as an anti-aliasing filter.

We can have multiple sensors, so I'm thinking of switching power to the INA and bridge separately to the opamp, and at least having provision for a 1Meg from the INA output to ground. Leaving opamp inputs floating seems like a bad idea, even if it is wired for unity gain...

As lgbeno said, low side switching is generally cheaper and easier to implement, provided your circuit will work correctly with low side switching.  High side switching is easy if the voltage you're switching is the same or lower than your control voltage, otherwise you probably need to use an Nmos to switch the Pmos gate so you can "insulate" your controller from the higher switched voltage.

Everything's 3.3V - and the CPU has a ton of I/O pin settings (open-drain, push-pull, various slew rates and so on). I'd be inclined to have a several-K resistor between gate and source, then a 100R from the gate to the CPU pin. Pull the pin low to turn on the hardware device.

Ah, excellent.  Then, if you turn on VREF to the bridge for, say, a few microseconds at a time, and sample only during that time, you have very little chance of interference from any source of noise -- uncorrelated noise then goes as 1/sqrt(N), so at worst, you could increase your sample rate a little (relative to the continuous, fully filtered and polished case) to compensate.

Vref is, sadly, the +3.3V power supply - the same power supply as the sensor, but unswitched. In theory, this shouldn't matter because the bridges are ratiometric (response tracks Vcc). We'll see...

Cheers,
Phil.

[tszaboo]

If it is only a few milliamp, is there a reason for use a mosfet as a switch at all? A logic gate can supply a few milliamp easily. You can just connect it to one of the microcontroller's GPIO. Or use an analog swtich, there are a lot in sot23 package which have less than an ohm resistance.