How do things change in the middle of a clock?

[NivagSwerdna]

I have been trying to reverse engineer a custom bit of 1980s silicon from an arcade game... pin 1 and pin 2 are external clocks... pin 1 normally gets 18 MHz... pin 2 normally gets a derived signal of 18MHz divided by 3 but with a 1:2 duty cycle... Anyway I have simulated the clocks in software to get approximately the same effect

Channel 6 is an output

How can Channel 6 change when either channel 0 (pin 1) or 1 (pin2) are not transitioning?  It's almost like it transitions exactly midway relative to channel 0?

The sample rate is 200Mz using my LA2016 analyser;  the synthesised input signal is approx 3 MHz so well below the sample rate.

Is it possible to derive a clock in the middle?

[Benta]

Look up "propagation delay".

[wasedadoc]

Look up "propagation delay".

I don't recall propagation delay being that long back then.

[tggzzz]

In a purely synchronous system, data signals can change at any time - provided the setup and hold times are not violated.

When gates were expensive, all sorts of "dirty" tricks were used. Clock gating has a long and inglorious history!

Don't forget to check you aren't doing an artefact caused by the LA sampling relatively too slowly.

[bson]

If Channel 0 is 18MHz, then a full cycle is 56ns, and a half cycle 28ns.
Channel 6 trails this by half of a half cycle, or about 14ns.

14ns isn't out of the ordinary for 1980s 74LS logic.  About the same as 74HC/74HCT.

A single gate output with significant fanout and hence capacitive loading will easily reach it.

[Benta]

Look up "propagation delay".

I don't recall propagation delay being that long back then.

If the top trace is 18 MHz, period is ~55 ns, high/low time ~28 ns. Propagation delay would then be around 10 ns to get the traces shown.

Why don't you do a bit of simple maths before shooting from the hip?

EDIT: well, bson pressed "Post" faster than me. 

[NivagSwerdna]

As I said above the clock is simulated in this example... it's around 3.7MHz (i.e. around 6 times less than normal operating frequency)

The transition between the low-high of the Channel 0 clock to the derived signal is large... 70ns

Maybe it is cumulative propagation delays then.. (I don't need to google that)... I guess 3 gates in series could produce something that large.

I will change the clock frequency and see if the delay stays the same... I cannot see how it would work though... since six times the clock...

[NivagSwerdna]

Here's an example using the real clock... 18.18MHz... with Channel 1 being the divided by 3 derived clock fed in to pin 2

Here we see Channel 6 changing 15ns after the low-high on Channel 0



Maybe I am correlating the wrong edges?

[NivagSwerdna]

OK... maybe that makes more sense... The output signal is way behind the input clock and the edge causing the transition is actually the one before I was considering...



So with a propagation of 70ns the output is more than a cycle of the fast clock late... sounds feasible

The circuit is probably something like this one.  Channel 6 is derived by a combination of bits from the shift register... maybe an AND of two bits.. so the clocks which appear on pins 1 and 4 of 9D are at least a NAND (9D), a NOR (4D), a shift (1P) and maybe 1M, and a combination... maybe that adds up to 70ns.

[Benta]

Why are you fixated on the low-high transition of the clock?
To my eye, the traces indicate high-low triggering. EDIT: so does the schematic you show. Propagation delay of the 74LS107 is 16 ns typ., which tallies with your first traces.

[joeqsmith]

Crap LA that you can't adjust the threshold for the logic family?  Personally, I would start with a scope and make sure what you are seeing with the LA is real.   

[Benta]

I think the OP already did that to get the 18 MHz results.
But then operator error stepped in by just downscaling all the signals to 3 MHz, which won't work. Propagation delays are constant and do not scale.

[tggzzz]

Looking at that schematic, there is no global clock; there is a series of local clocks, some of which are gated. Hence you have to be very careful defining which (local) clock you are observing. Timing will be well-defined relative to an IC's local clock, but poorly relative to other local clocks.

(Bloody difficult trying to refer to an IC that doesn't have a unique identifier, but...)

For the 'LS164 counters and anything hanging off their outputs, only the positive edge of the clock on pin 8 is important.

That pin 8 clock comes the 'LS74 clock, but negated and delayed by 1 or 2 poorly-defined gate delays (the two 'LS02s). And that is repeated before getting back to the crystal.

Hence if you are looking at the crystal, there will be several inversions plus poorly-defined delays between that and the 'LS164 outputs.

[NivagSwerdna]

If the top trace is 18 MHz, period is ~55 ns, high/low time ~28 ns. Propagation delay would then be around 10 ns to get the traces shown.

As stated "the synthesised input signal is approx 3 MHz".  With this set-up the period is 265ns.  By slowing the clock the delay should be more obvious because as stated it is constant.
If I take a rising edge then I see 70ns.

[NivagSwerdna]

Why are you fixated on the low-high transition of the clock?
To my eye, the traces indicate high-low triggering. EDIT: so does the schematic you show. Propagation delay of the 74LS107 is 16 ns typ., which tallies with your first traces.

To be clear again... the first traces have a clock manufactured in software at around 3.77MHz and any delay between CH0 and CH1 there is a manifestation of the S/W not hardware.  The 18MHz traces are real hardware.
My obsession is because I am speculating the same shift registers (2x LS164 and a LS74) like the schematic; note the actual custom silicon is black box to me but this is normally how it is done.  LS764 are +ve edge triggered.
On the schematic 9D and 4D effectively cancel each other out... the NAND meets a NOR.  The 6B pair can be ignored; that is a delay which is well expired in the examples.  So to me that makes +ve edges significant?

[tggzzz]

On the schematic 9D and 4D effectively cancel each other out... the NAND meets a NOR.  The 6B pair can be ignored; that is a delay which is well expired in the examples.  So to me that makes +ve edges significant?

Assuming the 'LS107 and 'LS74 don't insert clock edges, the circuit is

7A.7 -> delay1 -> 9D.6 -> delay2 -> 4D.4 -> delay3 ->1 P.* -> delay4 -> 1N.8 -> delay5 -> 1L.*

Each delay? is poorly defined, e.g.
delay1 is 8ns (typ) to 22ns (max), with no (min)
delay3 is 17ns (typ) to 32ns (max), with no (min)
etc

All of those poorly defined and variable delays add up, so it can be seen why clock gating is problematic.

[Benta]

All of those poorly defined and variable delays add up, so it can be seen why clock gating is problematic.

Yes, it's a very old-fashioned and "dirty" design. Today it would be done using synchronous clocking, although that demands a bit more logic (unimportant now, but significant back then).

[coppice]

(Attachment Link)

I have been trying to reverse engineer a custom bit of 1980s silicon from an arcade game... pin 1 and pin 2 are external clocks... pin 1 normally gets 18 MHz... pin 2 normally gets a derived signal of 18MHz divided by 3 but with a 1:2 duty cycle... Anyway I have simulated the clocks in software to get approximately the same effect

Channel 6 is an output

How can Channel 6 change when either channel 0 (pin 1) or 1 (pin2) are not transitioning?  It's almost like it transitions exactly midway relative to channel 0?

The sample rate is 200Mz using my LA2016 analyser;  the synthesised input signal is approx 3 MHz so well below the sample rate.

Is it possible to derive a clock in the middle?

If you are confused by something like this you really need to stop using a logic analyzer, and look at the actual signals. The logic analyzer takes away all the dynamics, and can greatly confuse the beginner. The reality is there is no digital circuitry. All circuitry described as digital is analogue circuitry trying to look digital. Look at the real signal dynamics with an oscilloscope, and the way all the little delays, slow edges and other not-quite-digital aspects of real signals work out will make sense.

[NivagSwerdna]

I don't really understand the relevance of synchronous clocking in this context. All three parts of the LFSR share a common clock.

The LS107 is only relevant in the sense that it derives the divide by three logic but the two clocks into 9D are then NANDed to give a clock which is the 18MHz clock enabled by the other divide clocked but the edges are still really defined in terms of the 18MHz clock?

The part that is asynchronous is the propagation through the shift registers and any subsequent combinatorial operation.

I will have to dig out my notes but I think CH6 is derived from two output bits of the shift registers ANDed together.

[NivagSwerdna]

With my scope the traces look a lot more scary...  (I only have a 2CH scope)

Fast Clock CH0


Slow Clock CH1


Both Clocks


Fast Clock and Derived signal


Fast Clock and Derived signal

[NivagSwerdna]

You have to use your imagination on those traces but I think these are the intended clocks...



So the shift registers are ticked twice for each pixel (6MHz Pixel Clock).   

The lower trace is what I think should come out of 4D... if I had one... mine is deep in the custom chip.

[bson]

Both Clocks
(Attachment Link)

The cyan trace shows significant capacitive loading...  It doesn't hit the high TTL threshold until the next rising clock edge!

Sorry, but I just can't figure out how images work on this forum software.

[NivagSwerdna]

The cyan trace shows significant capacitive loading...  It doesn't hit the high TTL threshold until the next rising clock edge!

I agree. Maybe that explains why my attempts to reverse engineer this have been so tricky so far...