A resistor in series at the load end will not hurt. It also is unlikely to help much. The terminating load impedance will be the 100 ohms in series with a few pf of load from the gate. The 100 ohms and a 0.1 uf will work to a much lower frequency.
You only need C >= 2.5 x Cstray, whatever that is (~50-100pF/m of line?).
0.1uF is so large, you are likely to get pattern-dependent bit errors, because the input is being loaded to voltages between V_IH(min) and V_IL(max).
Source termination is better than load termination, for point-to-point interconnects (e.g., USB, PCIe). For bus interconnects, you often have no choice but to do load or double termination (e.g., RS-485 multi master). Noisy environments give some advantage to load termination, because then you can apply CM filtering to improve immunity.
Note that a logic output pin has some series resistance, usually around 30-70 ohms, so you don't need a full 100 ohms to match it. 33-68 ohms is typical.
If your line length and bit rate are small, you can save more EMI by using an excessively large value (>300 ohms?), or filtering even more (extra C, ferrite bead, etc.).
Tim