how to design fast bench supply with CC and CV?

[David Hess]

Does anyone remember the big, brown Motorola semiconductor data book?

I have a brown Motorola book sitting here in front of me but it dates from 1984.  It shows a 0.8MHz minimum 2N3055A with a straight SOA curve and no secondary breakdown and a 2.5MHz minimum 2N3055 with secondary breakdown starting at 40 volts.  What I have not seen is the SOA for the earlier 2N3055 which was even slower, 0.2 MHz?

My workstation is in pieces at the moment or I would scan them in and post them but I am sure the Motorola book is available online.  Somewhere I have an older one with a blue cover I think.

[not1xor1]

[...]
8. Performance... Well, how about recovery time from 0 to 100% load and back? Say, in less than 20us. Also fast CV/CC switch without glitches. Not sure how to define that.

I might be wrong, but while I see a clear advantage in fast switching from CV to CC I can't see any usefulness in real life in a fast recovery from 100% load (i.e. overload). 

I think the most important features are:
-1) fast CV->CC switch with as little over-current spike as possible
-2) CC-CV switch with no over-voltage spike

In various different circuits I've simulated in past I've got the feeling that the worst overload recovery (i.e. highest relative value voltage spikes) occur when output voltage is set at a few volts (1-2V and below).
Besides that anti-windup diodes (like in those blackdog circuits) do affect load regulation due to leakages (at least in simulation).
For instance simulate a 5-95% load variation and check output voltage with and without the windup diodes.

[udok]

Just my thoughts on your requirement list:

6. Stability with minimum output capacitance

=> That should be easy as it is only shunting the internal capacitor.

7. Stability with large output capacitance

=> That could be very difficult.  Especially with modern low ESR types.
  Add inductors to the list and you have enough work for the next year.

I would not be surprised if many lab power supplies have serious overshoots or oscillate with some
combinations of modern Polymers with low ESR.

Maybe that is the real reason, why commercial supplies are not faster than 50 - 100 us,
or maybe they still continue to copying the old HP schematics.
The old HP and Harrison designs do not mention stability concerns or calculations.
The were build by experimenters and work very well with the components of the 60.
But they use a lot of positive feedback for bootstrapping and this could cause troubles
with faster designs.

8. Performance... Well, how about recovery time from 0 to 100% load and back? Say, in less than 20us. Also fast CV/CC switch without glitches. Not sure how to define that.

=> A awful lot of more work.


x. Bonus points if PSU can:
1. Sink current
1. Bipolar

=> This is a SMU and that greatly complicates the design and the price
     The usefulness  for a power supply is limited.


1. Multiple voltage ranges, but I don't really need steps more than 1mV. But nice to have .

=> Not necessary with 16 bit DACs

1. True remote sensing.

This is necessary with rear connectors


Why not build a simple proven design like the NG304, schematic is on page 12:
https://www.mikrocontroller.net/attachment/412953/DBL_BEHA_NG304_MANUAL_DEUTSCH.PDF
(in German, but schematic is very simple)

I have the impression that you have never build even such a simple design?


y. I would like to build a high-precision, high-performance power supply. How would I do that?

=> Study the schematics of the older HP/Harrison/RohdeSchwarz/Kepco/TTi and understand them.
If you then still want to improve them, then simply do it.

Switching from CV/CC and back is only a minor detail in this venture.
First you need a clear understanding how stability in this supplies depends on the output load.

[Kleinstein]

Stability with large capacitive (and low ESR) load is the difficult part. For voltage regulation a inductive load is not a problem - it may though lead to some overshoot in designs with a large capacitor at the output. Aiming for low internal capacitance makes this point less of a point. An inductive load can be an issue in CC mode. However real world inductors tend to be less ideal than some capacitors especially in the lower frequency range (e.g. 10 kHz) where things could become tricky.

The large low ESR capacitors (e.g. polymer electrolytic) still tend to have quite some loss - so they may not be so bad as one may think. The tricky part could be more like some 1000 µF as C0G or PP film cap, but this is still a little on the rare side.

To get get good good stability one may even need at least some sinking (at least limited) capability. Other wise the transition towards the output stage all the way off can easily cause an instability problem. This can be fixed with sinking capability - but may need compromises in the way the negative current is limited (e.g. no fixed time independent limit there).
Stability in the linear / small signal range is still relatively simple - here the theoretical background is well founded. The tricky part comes with stability in the large signal area when some regulator parts hit limits (e.g. transistors turn all the way off). With the control going beyond all the way off will add delay when turning on again and this increases overshoot and can cause oscillations.

[udok]

FYI: Attached are the stability margins for CC and CV operation of the HP6624.

When the regulator loop is running out of gain, the output cap is providing the energy
and the ESR of the output cap is dampening the resonances.

With low value capacitors the regulator needs a larger bandwidth, and the
output cap is lower and often of ceramic type with low ESR.

This could be a problem because the remaining total ESR is not enough to dampen resonances.

A lot of PCBs today use only ceramic caps at the input, because they are small and cheap,
but this could lead to large overshoots.  Some engineers even put a ferrite bead in front,
and build a series resonance converter for the input voltage, maybe to test the voltage limits of the chips.

[xavier60]

This is the post regulator in my 20 amp bench supply. For fast current limiting, the CC op-amp operates in open loop until it takes control of the MOSFET's Gate from the CV op-amp. Then Q2 turns on, closing the feedback loop via C1.
The precharge on C1 determines the amount of allowed current overshoot, about 50%, less at higher CC settings. The precharge is set by the supply's micro-controller according to the present CC setting.

Extra: In the design of a second smaller bench supply, the CV op-amp's compensation is taken from the ORing node ,suggested by Kleinstein.
This greatly reduces voltage overshoot caused by when the supply transitions from CV to CC and to CV again before the output voltage drops by much.

[udok]

Xaviers and Kleinsteins circuits are clever improvements for a SMU.

But i do not quite understand why a quick transition from CV to CC mode is important for a power supply.
In a bench power supply the CC mode is mainly a safety feature to limit destructive energy.

And anyway the CC mode kicks in after the output capacitor has depleted, which is many microseconds
later.

And a transient increase of output current does not harm and is often a very desirable feature.
Rohde & Schwarz even advertises power supplies as "large current pulse capable".

In my opinion there is no need for a fast transition from CV to CC, and these
circuits may even severely limit the usefulness of the power supply in practice.

Normally the CV error amplifier is build 5-10x faster than the CC amplifier, and therefore
the voltage does not overshoot for a CC to CV transition.

This is the expected behavior of a bench power supply and there is no need to improve.

The one exception are absolute beginners, who mix up a power supply with a current source.

SMUs on the other hand have no output capacitors but are only unconditionally stable with no more than 20 nF load in CV mode.
They are designed as excellent CC sources.

But modern SMUs use fast CMOS switches for the range switching, controlled digitally by FPGA.
Some SMUs even implement the control loop in FPGA and there is no need for clever analog solutions  anymore.

Long ago HP build constant current power supplies for device breakdown testing (HP 6177, 6181, and there was a 300 Volt model too).
These devices used a current regulation amplifier which *never* goes into saturation.
If the output voltage limit is exceeded, a shunt regulator shunts current to ground until the voltage
stays in the CV limit.
They have two nested regulation loops, a fast one for CC and a slower one for CV.
These are excellent devices for LED testing or transistor breakdown testing.

And what is the use case for a fast response power supply?  And what is fast?

[xavier60]

I like fast limiting mainly to protect the power supply itself. My designs intentionally allow some current overshoot.
Curiously, my Agilent U8002A outputs virtually unlimited current for 100us or so when short circuited. It has no fast current limiting at all.
My 2 designs that I regularly use on the bench have a CV load response that's unnecessarily fast at about 10us, just because.
All of the stuff I work on is normally powered by long power cables anyway so speed is not important at all.
My Agilent U8002A is about 30us.
I think minimizing voltage overshoots at low voltages is important as it could cause a load to be damaged without being certain why.

[iMo]

I want a 30V/3A PSU which will not destroy a red LED when set to 20mA and 30V..

[exe]

And what is the use case for a fast response power supply?  And what is fast?

Good question. I like playing with small circuits made of sensitive components. I often do wiring errors, or use damaged components (without knowing that), that often lead to high fault currents. For this reason I'd like to minimize damage. One practical situation I had is I damaged my ne5532 because I connected my power supply to it's input in wrong polarity. The opamp survided, but the input protection diode was damaged, this lead to excessive input current. I wonder if a faster power supply with less capacitance could prevent the damage.

For the cases when I don't need fast response, I'd like to use bigger output cap.

What is fast? A few tens of us I'd consider fast. I think what I really want is to figure out how to avoid long opamp recovery time and big output swings when changing between modes. This will make me feel good. Ah, no overshoots, as I mainly work with low-power ICs.

[exe]

I want a 30V/3A PSU which will not destroy a red LED when set to 20mA and 30V..

I can't speak for 30V, but for 17V I had hard times destroying a red led. I tried quite significant output capacitance (afaik some hundreds of uF), it survived. So, either this is not a big challenged, or I have an outstanding diode. I'll repeat the test tonight with a few diodes at hand and report here.

[iMo]

I want a 30V/3A PSU which will not destroy a red LED when set to 20mA and 30V..

I can't speak for 30V, but for 17V I had hard times destroying a red led. I tried quite significant output capacitance (afaik some hundreds of uF), it survived. So, either this is not a big challenged, or I have an outstanding diode. I'll repeat the test tonight with a few diodes at hand and report here.

Try it with a) wire a red LED to the PSU and switch the PSU on/off several times (PSU set 20mA/30V), b) while PSU on (PSU set 20mA/30V) connect the LED to the PSU few times (forward biased).

[Zero999]

Xaviers and Kleinsteins circuits are clever improvements for a SMU.

But i do not quite understand why a quick transition from CV to CC mode is important for a power supply.
In a bench power supply the CC mode is mainly a safety feature to limit destructive energy.

And anyway the CC mode kicks in after the output capacitor has depleted, which is many microseconds
later.

And a transient increase of output current does not harm and is often a very desirable feature.
Rohde & Schwarz even advertises power supplies as "large current pulse capable".

In my opinion there is no need for a fast transition from CV to CC, and these
circuits may even severely limit the usefulness of the power supply in practice.

Normally the CV error amplifier is build 5-10x faster than the CC amplifier, and therefore
the voltage does not overshoot for a CC to CV transition.

This is the expected behavior of a bench power supply and there is no need to improve.

The one exception are absolute beginners, who mix up a power supply with a current source.

A current source is a type of power supply. It would be handy to have a general purpose power supply which is designed to be both a good current source for powering things such as LEDs, as well as a voltage source.

As long as it's stable with a large output capacitance and the voltage doesn't overshoot too much, I don't see why the transient response of the power supply is that important. Poor voltage transient response can easily be straightened up with a large capacitor. Any load, which requires a good transient response, such as a microcontroller or FPGA, should have lots of supply decoupling, to ride out any troughs.

Good constant current regulation can be achieve with a large inductor, but large, high quality inductors are expensive, compared to, large, high quality capacitors, which are cheap.

I appreciate it's not possible for a power supply to both have a good CC and CV modes. One fix would be to add a switch to select between optimal CV and CC operation.

By the way, please refrain from using a new line each time, allow the forum to word wrap: it's so much easier to read.

[exe]

Try it with a) wire a red LED to the PSU and switch the PSU on/off several times (PSU set 20mA/30V), b) while PSU on (PSU set 20mA/30V) connect the LED to the PSU few times (forward biased).

Oh, just saw your message after I recorded the video. So, I didn't set to 20mA, but to ~10mA because I think 20mA is too much for leds. And it's not a big deal anyway, I don't think 20mA or 10mA make any difference in the test. I did power on/off test separately, all leds survived except (spoiler alert!) the one that was fried, it remained dead. So, here is how the led torture test went:



One led died even at 15V, although survived first test, but not subsequent. Rest were fine. So, the led does matter too . Also shows there is a room for improvement in this power supply.

[exe]

Why not build a simple proven design like the NG304, schematic is on page 12:
https://www.mikrocontroller.net/attachment/412953/DBL_BEHA_NG304_MANUAL_DEUTSCH.PDF
(in German, but schematic is very simple)

(sorry, didn't notice your post).

Nice design, I've built a prototype of it (blackdog's version of it). The only concern is voltage set resistor creates parasitic current. It's small but I'd like not to have. I didn't figure how to solve this. May be the easiest option would be to have reference ground-referenced, and control it via an optocoupler or something. Or just make this resistor big so the error current is small...

Starting with a clean simple design and add features is that what I tried to do, but no luck there. Most "golden" designs use isolated auxilary voltages, pots, and panel meters. This greatly simplifies design.

[David Hess]

6. Stability with minimum output capacitance

=> That should be easy as it is only shunting the internal capacitor.

I think he means the internal output capacitance should be minimized.

7. Stability with large output capacitance

=> That could be very difficult.  Especially with modern low ESR types.

I would not be surprised if many lab power supplies have serious overshoots or oscillate with some
combinations of modern Polymers with low ESR.

There are at least two solutions for solving the problem of unconditional stability into a capacitive load:

1.  Conventional frequency compensation typically privides about 45 degrees of phase margin.  The open loop output series resistance combined with the output capacitance adds phase lag further lowering phase margin.  The output capacitor's ESR adds phase lead which increases phase margin so that is why low ESR output capacitors are especially troublesome and require an added series resistance for stability.

The solution which regulators use to allow operation with large low ESR output capacitors is to take AC feedback from before the open loop output series resistance.  On an integrated circuit, a special transistor structure can be used to do this however a separate fixed resistance also works. This resistance produces the same result as increasing the ESR and is in series with the capacitor but it located in a different place and the amplifier's low frequency DC gain removes its effect on regulation.

2. Another solution implied above is to use frequency compensation which has less than the common 90 degrees of phase lag.  For instance replace the capacitor in the commonly used Miller integrator with a series of RC networks which provide -3 dB/octave of roll-off instead of -6 dB.  The trade off here is poorer frequency response but the results are better under adverse conditions.  I have seen this method used with ATE (automated test equipment) pin drivers.

[udok]

Why not build a simple proven design like the NG304, schematic is on page 12:
https://www.mikrocontroller.net/attachment/412953/DBL_BEHA_NG304_MANUAL_DEUTSCH.PDF
(in German, but schematic is very simple)

(sorry, didn't notice your post).

Nice design, I've built a prototype of it (blackdog's version of it). The only concern is voltage set resistor creates parasitic current. It's small but I'd like not to have. I didn't figure how to solve this. May be the easiest option would be to have reference ground-referenced, and control it via an optocoupler or something. Or just make this resistor big so the error current is small...

Starting with a clean simple design and add features is that what I tried to do, but no luck there. Most "golden" designs use isolated auxilary voltages, pots, and panel meters. This greatly simplifies design.

The current voltage set current is only a minor error compared to the error introduced by driving the power transistor.  The base current goes
through the current measurement shunt resistor too.
The cure to this problems is to pin the floating ground of the bias supply to the output of the power transistor *before* the shunt resistor.
In this way all the leakage currents are not measured by  the shunt resistor.
This is done in "precision" power supplies, but it is more work because if you do this, you cannot measure the output voltage without a true differential
amplifier.  Often it is easier to provide a current offset trimmer, and keep the leakage currents constant and down to a minimum.

Today you cannot build and sell a bench power supply which has less than 30 Volt and 3 Ampere output capability, because the
market is dictated by the cheap china HP replicas.
At the same time modern electronics does not need more than 100 mA @ 3.3 Volt.  This is a problem 100 mA are only 3% of the 3 Ampere range,
and the leakage currents scale with max current.

[udok]

7. Stability with large output capacitance

=> That could be very difficult.  Especially with modern low ESR types.

I would not be surprised if many lab power supplies have serious overshoots or oscillate with some
combinations of modern Polymers with low ESR.

There are at least two solutions for solving the problem of unconditional stability into a capacitive load:

1.  Conventional frequency compensation typically privides about 45 degrees of phase margin.  The open loop output series resistance combined with the output capacitance adds phase lag further lowering phase margin.  The output capacitor's ESR adds phase lead which increases phase margin so that is why low ESR output capacitors are especially troublesome and require an added series resistance for stability.

The solution which regulators use to allow operation with large low ESR output capacitors is to take AC feedback from before the open loop output series resistance.  On an integrated circuit, a special transistor structure can be used to do this however a separate fixed resistance also works. This resistance produces the same result as increasing the ESR and is in series with the capacitor but it located in a different place and the amplifier's low frequency DC gain removes its effect on regulation.

2. Another solution implied above is to use frequency compensation which has less than the common 90 degrees of phase lag.  For instance replace the capacitor in the commonly used Miller integrator with a series of RC networks which provide -3 dB/octave of roll-off instead of -6 dB.  The trade off here is poorer frequency response but the results are better under adverse conditions.  I have seen this method used with ATE (automated test equipment) pin drivers.

The problem is more complicated than it first seems, because the output impedance should be as low as possible *and* the power supply
should handle all loads well, including 3 meter of cables with 100 nF ceramic capacitor at the end. The 100 nF case needs a few ohms of damping.

The idea to take feedback before the current measurement shunt does not work as it increases the output impedance from <1mR to at least 0.1-1 Ohm.

Form the user viewpoint the most important feature of a power supply is to provide a constant voltage with any load as long as the current is
within the limits for 99% of the time.  Because there is no universal solution to this problem power supplies used to have over voltage protection circuits.

The second option is much work to implement and has in 100% of the test cases mediocre performance, which is not competitive.

[exe]

Attaching the schematic of that anti-soar clamp that I advertised earlier. Hope posting it here falls under fair use.

Here's my shot at the fast current limit.

Thanks a lot for your effort and time, learning this design. Kleinstein's design will be next .

The current voltage set current is only a minor error compared to the error introduced by driving the power transistor.  The base current goes
through the current measurement shunt resistor too.

I don't understand this part. If using an NPN (or darlington/sziklai equivalent) transistor as emitter follower, all current goes into the load. So, no problem there.

The error from voltage set current is... well, depends on the resistor values and control/output voltages, but the thing is, it varies with the output voltags. So, if power supply in CC mode, then output current varies with the load, this greatly reduces output impedance. How greatly?

For example, I have voltage set from DAC in the range of 0-2.5V. Say, I need maximum voltage of 15V, so I need 15V/2.5=6x gain. If I use 10k and 2k resistors, then the parasitic current is (I=U/R) (at maximum output voltage of 15V): 15/10k=1.5mA. Sort of a lot... Probably I could raise resistor values, I was just worried about noise. I can bypass the lower resistor, but then I won't be able to quickly set voltage, i.e., use my power supply as AWG .


A solution could be to have ground-referenced voltage, and somehow with some level-shifting set current on a high side. Like on the included schematic. I discarded that idea. One of problem is that it didn't want to start, so I added this startup resistor across pass transistor. The second is I cannot use a clamping diode with this design (this is the only type of clamping I mastered so far, but I'm studying other proposed methods).

[Kleinstein]

Wether the base current contributes to the output current and is measured correctly depends on how the ground of the floating supply is connected. The floating supply type regulators can cause quite some confusion there. It gets even more tricky with extra sense inputs.

The plan shown is actually not that different from the simulation version I showed, just with more details and a MOSFET power stage.

I don't like the way the output voltage is set - this is more like the old way from the 1970s, with a more or less constant current from the reference and than a variable resistor. This way the variable divider in the feedback path changes the compensation is the voltage is adjusted. It is usually better and with digital control also the logical way to adjust the reference voltage side and use a fixed divider in feedback.

Using part of the AC feedback from before the current shunt is viable option. This adds some resistance (e.g. 0.1-1 Ohms) to the output impedance, but only in the higher frequency area where it is wanted to dampen oscillations.

[exe]

I might be wrong, but while I see a clear advantage in fast switching from CV to CC I can't see any usefulness in real life in a fast recovery from 100% load (i.e. overload). 

That's just a figure of merit, it doesn't come from a practical scenario. I'm open for suggestions, including those you mentioned below. The reason it starts not from 5% or 10% load is because in my designs I most of the do some sort of pre-loading, it's when there is a current sink from the output stage. This improves regulation under light load.

I think the most important features are:
-1) fast CV->CC switch with as little over-current spike as possible
-2) CC-CV switch with no over-voltage spike

In various different circuits I've simulated in past I've got the feeling that the worst overload recovery (i.e. highest relative value voltage spikes) occur when output voltage is set at a few volts (1-2V and below).
Besides that anti-windup diodes (like in those blackdog circuits) do affect load regulation due to leakages (at least in simulation).
For instance simulate a 5-95% load variation and check output voltage with and without the windup diodes.

Oh, wow, I see you are speaking from experience (at least with simulators) . I had issues with diodes too, esp. with LEDs. Definitely rf schottky worked better in the simulator. I'm so happy that I have no shortage of high-performance parts (except some good parts from the past that extinct). It's not like 20 years ago I was limited what was in my local store.

[David Hess]

7. Stability with large output capacitance

=> That could be very difficult.  Especially with modern low ESR types.

I would not be surprised if many lab power supplies have serious overshoots or oscillate with some
combinations of modern Polymers with low ESR.

There are at least two solutions for solving the problem of unconditional stability into a capacitive load:

1.  Conventional frequency compensation typically privides about 45 degrees of phase margin.  The open loop output series resistance combined with the output capacitance adds phase lag further lowering phase margin.  The output capacitor's ESR adds phase lead which increases phase margin so that is why low ESR output capacitors are especially troublesome and require an added series resistance for stability.

The solution which regulators use to allow operation with large low ESR output capacitors is to take AC feedback from before the open loop output series resistance.  On an integrated circuit, a special transistor structure can be used to do this however a separate fixed resistance also works. This resistance produces the same result as increasing the ESR and is in series with the capacitor but it located in a different place and the amplifier's low frequency DC gain removes its effect on regulation.

2. Another solution implied above is to use frequency compensation which has less than the common 90 degrees of phase lag.  For instance replace the capacitor in the commonly used Miller integrator with a series of RC networks which provide -3 dB/octave of roll-off instead of -6 dB.  The trade off here is poorer frequency response but the results are better under adverse conditions.  I have seen this method used with ATE (automated test equipment) pin drivers.

The problem is more complicated than it first seems, because the output impedance should be as low as possible *and* the power supply
should handle all loads well, including 3 meter of cables with 100 nF ceramic capacitor at the end. The 100 nF case needs a few ohms of damping.

The idea to take feedback before the current measurement shunt does not work as it increases the output impedance from <1mR to at least 0.1-1 Ohm.

No, DC voltage low frequency feedback is taken *after* the added series resistance so the output resistance is divided by the open loop gain.  The same thing happens to reduce the inherent output resistance of the output stage but in this case, the current shunt and any deliberately added series resistance is included as well.

The change in this case is to move the resistance which would be placed in series with the low ESR output capacitor to aid stability to a point where it is before low frequency feedback is taken so its effects on DC accuracy are removed but since AC feedback is taken before the resistor, it still serves to improve stability.  The result is that the high frequency output impedance is dominated by the low ESR output capacitor and the low frequency output impedance is dominated by the series resistance, up to the feedback point, divided by the open loop gain.

This is how integrated regulators designed to operate with ceramic output capacitors work but they can use a special output transistor structure to take AC feedback from before some of the output resistance of the output transistor.

The second option is much work to implement and has in 100% of the test cases mediocre performance, which is not competitive.

The second method is still higher performance than if the regulator relied on dominant pole compensation to make a low ESR output capacitor stable.  Dominant pole compensation would provide a -6dB/octave roll-off but would need an even lower cutoff frequency.

[udok]

No, DC voltage low frequency feedback is taken *after* the added series resistance so the output resistance is divided by the open loop gain.  The same thing happens to reduce the inherent output resistance of the output stage but in this case, the current shunt and any deliberately added series resistance is included as well.

Ok, i did not get it that you only take the AC feedback from the point before the shunt resistor.  This should work, but you have to design for
the worst case capacitor (largest one). 
If the largest cap is 100 mF and Rout is 0.1 Ohm, you pole is at 16 Hz.   This is not promising.

The second method is still higher performance than if the regulator relied on dominant pole compensation to make a low ESR output capacitor stable.  Dominant pole compensation would provide a -6dB/octave roll-off but would need an even lower cutoff frequency.

The -6dB/octave gives you a very clean impulse response.  This is an advantage, but i think that the method with the -3 dB/octave would work too.

If you have 100 dB open loop gain at 1 Hz, you have to get down to 0 dB at about 100 kHz. With the -3 dB/octave method you need a -12 dB/octave
region somewhere or you will not be down at at 0 dB@100kHz.  Could be complicated.

But anyway, it is getting too complicated for my brain here.

[udok]

Quote from: udok on April 13, 2020, 05:34:19 pm

    The current voltage set current is only a minor error compared to the error introduced by driving the power transistor.  The base current goes
    through the current measurement shunt resistor too.


I don't understand this part. If using an NPN (or darlington/sziklai equivalent) transistor as emitter follower, all current goes into the load. So, no problem there.

If you need precise current measurement the base current is one of the main error sources in the classical circuit which blackdog uses.
The base current flows through the current shunt and depends on transistor beta which is dependent on temperature and collector-emitter voltage.
This circuit is not designed for precision current measurement, but this does not matter in most cases because a bench power supply is a voltage source.

[Kleinstein]

Ok, i did not get it that you only take the AC feedback from the point before the shunt resistor.  This should work, but you have to design for
the worst case capacitor (largest one). 
If the largest cap is 100 mF and Rout is 0.1 Ohm, you pole is at 16 Hz.   This is not promising.


The -6dB/octave gives you a very clean impulse response.  This is an advantage, but i think that the method with the -3 dB/octave would work too.

If you have 100 dB open loop gain at 1 Hz, you have to get down to 0 dB at about 100 kHz. With the -3 dB/octave method you need a -12 dB/octave
region somewhere or you will not be down at at 0 dB@100kHz.  Could be complicated.

For largest considered capacitance one can compromise: there are 2 regions with a large external cap: one usually does not want the supply to oscillate with any reasonable external cap, but one does not need good performance with a really large cap. So it's more like not oscillating up to some 100 mF, and low ringing up to a lower limit like 100 µF low ESR or 1000 µF with normal ESR.

The simple dominant pole compensation with -6dB/octave gives an inductive output impedance. So with an external or internal low ESR cap, one has a resonant circuit and thus quite some ringing.
One may have the 100dB or similar loop gain not at 1 Hz but only well below that.  Still it gets better with a steeper part in between and than a little less than the -6dB for the higher frequencies / cross over region so that the output does not behave like an ideal inductor.