| Electronics > Projects, Designs, and Technical Stuff |
| How to even start routing this? |
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| Unixon:
--- Quote from: T3sl4co1l on August 02, 2019, 09:26:06 am ---Consider enlarging the board, or using TSSOP devices (which I guess at this speed, should be 74HC for some, and AC or LVC when needed?). --- End quote --- SOIC packages have an underestimated and very useful feature: the ability to let traces go between pads on the same precision class board. While TSSOP packages occupy less space, they potentially make routing harder. |
| spudboy488:
--- Quote from: tautech on August 02, 2019, 09:04:49 am ---Oh and I forgot, for dual, triple, quad and hex packages don't forget you can reassign gates to make routing easier. --- End quote --- The same holds for signals going through bus devices. For example, you don't have to keep D0 through D8 aligned through an 8-bit buffer/latch/etc. as long as the same order is applied on the other side. |
| dmills:
Also, (Static) RAM can usually freely swap address lines and data pins which can be VERY helpful, and is often forgotten.... 4 Layers for me (It is pretty much my default position these days). Regards, Dan. |
| ejeffrey:
--- Quote from: tggzzz on August 02, 2019, 08:33:09 am --- If you do, make one layer a solid ground plane and another a solid Vcc plane. If they are inner planes then it is easier to probe and modify signals. If they are outer planes then EMI problems will be minimised. Choices, choices :) ) --- End quote --- Hardly a choice. The EMI advantage of outer planes is hardly worth the ease of debug and tracing for what I assume is a one off. Plus for a project that is basically intended to show off old school 74 series logic design, it hard to give up the appearance of a nicely routed board for solid planes. |
| voltsandjolts:
4 layers will save your sanity. pcbshopper.com is your friend. (no affiliation). |
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