Electronics > Projects, Designs, and Technical Stuff
How to even start routing this?
Joanna_H:
--- Quote from: mikeselectricstuff on August 03, 2019, 10:07:22 pm ---Nice thing about the XO2 is it has onboard config memory, core voltage regulator and also an oscilllator, so minimal extra parts. A few package options from QFN32 to QFP144.
--- End quote ---
Yeah, like the QFP144, enough I/O to get things going.. as I'm trying to create a "modular" cpu that you can see what each bit is doing this could be a nice path. But I think I'll need a few of them as I'll need quite a few control lines. Even so, it's worth exploring as an option :D
NivagSwerdna:
I was trying not to mention FPGA as it seemed to go against your design goals and I was assuming this was a 5V retro project. Checkout TinyFPGA for design ideas if you are going that route.
Mike has replied and has a lot more experience than me but XO2 does come in small configurations or there is ICE40.
Have fun
rstofer:
Back to routing:
If any of the devices are memory chips, you don't have to keep strict alignment between A0->A0, A1->A1, etc. You can hook the address lines in any sequence. The only thing that happens is that logically adjacent address are spread around in the memory.
Same deal for data lines. D0 doesn't have to be right next to D1.
This turns out to be a real big deal when working with memory and MCUs.
ETA: This may cause problems with DDR memory but is often used for SRAM.
Joanna_H:
--- Quote from: NivagSwerdna on August 04, 2019, 01:19:20 pm ---I was trying not to mention FPGA as it seemed to go against your design goals and I was assuming this was a 5V retro project. Checkout TinyFPGA for design ideas if you are going that route.
Mike has replied and has a lot more experience than me but XO2 does come in small configurations or there is ICE40.
Have fun
--- End quote ---
Yeah, my original goal was all TTL, but with board space, number of components, etc. etc.. The cost would become silly.
Joanna_H:
Thanks for the FPGA suggestion, this is fun. Different way of thinking about it all, but I should be able to achieve the same goal. A CPU that you can monitor every part of it and see how it works :D
Thanks.
Verilog is a bit interesting though....... Something new to learn.
Still, having fun.. AddressLineDriver / Program Counter and a few other bits done so far.
The second jump test is an inpage jumping test, which gives a data bus size jump range (16bit in this example) costing only 1 cycle.
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