Locking the clocks is the best way to avoid the problem. If you have the timing resolution on the SAI module you could, with some care, trim the clock rate to match the as-received uart data rate (you'd need to filter out as much jitter as possible, since there will likely be a fair bit of uncertainty introduced by the software on both sides of the uart link). If you can't hit an exact phase match then you may have to dither the clock rate, as long as that won't screw up the output too much. If you don't have enough clock resolution on the output, or can't tolerate changes in the output clock rate, the easiest solution would be to skip or duplicate a sample whenever the pointers move out of sync. You could also fully resample the buffer, interpolating samples at the new clock rate from the samples at the old clock rate, but that's probably not worth the trouble for most applications.