Electronics > Projects, Designs, and Technical Stuff
How to protect analog inputs on low power device from overvoltage?
NotAVirus:
--- Quote from: jbb on December 13, 2019, 06:29:01 am ---Ah, nice. I was thinking about the PNP common base clamp trick myself, and I’m glad to see it’s a known method.
--- End quote ---
yea. had a little eureka-moment, finding this trick. ;)
--- Quote from: Berni on December 13, 2019, 06:49:21 am ---the little known depletion mode MOSFET.
--- End quote ---
didn't knew this things existed. This app-note from Infineon was interesting. https://www.infineon.com/dgdl/Infineon-Application_Note_Applications_for_Depletion_MOSFETs-AN-v01_00-EN.pdf?fileId=5546d4624cb7f111014cd63d1a197d94
I have done some modifications on my initial design. As David Hess suggested, M1 is not required if the impedance on the PNP-base is low enough. This can be done by adding an op-amp buffer between the voltage divider and PNP-base. I have also removed the isolation diode(D3) as this is not needed. When protecting several inputs one could simply add a PNP-transistor to each input, and connect all the base-pins to one single op-amp. Removing one isolation diode should give the circuit a sharper clamping voltage.
DBecker:
Bias the clamping rail. That doesn't mean that you need to push much current through the zener. You aren't trying to get a stable voltage there, just minimize the loading on the signal lines. A zener is more appropriate than a TVS because of the sharper curve.
Most of the other solutions suggested seem a bit overkill, costing in components, board area and complexity.
David Hess:
--- Quote from: NotAVirus on December 13, 2019, 09:02:01 pm ---
--- Quote from: Berni on December 13, 2019, 06:49:21 am ---the little known depletion mode MOSFET.
--- End quote ---
didn't knew this things existed. This app-note from Infineon was interesting. https://www.infineon.com/dgdl/Infineon-Application_Note_Applications_for_Depletion_MOSFETs-AN-v01_00-EN.pdf?fileId=5546d4624cb7f111014cd63d1a197d94
--- End quote ---
Depletion mode MOSFETs have been available almost from the beginning and before them, JFETs could be used and there were even high voltage JFETs. Their poor cost and availability tends to limit them to more expensive applications.
A resistor added in series with the source before the gate connection allows lowering the current limit at the expense of raising the series resistance.
Their flaw, if it can be considered that, is that they have no overload capability above their breakdown voltage at all. Which reminds me that another useful current limiting device is a small high voltage incandescent light bulb. The low thermal mass of the filament allows much faster response than a PTC thermister or polyfuse and in the worst case, it acts as a pretty good fuse.
T3sl4co1l:
Nice thing about high voltage DMOS is you can afford enough voltage range to use a frickin' MOV to handle ESD/surge. (No need for leaded parts, MOVs come in small chip packages too -- the low ESL is especially good for ESD.)
If you're using a biased clamping rail, note that you need capacitors to absorb ESD. Something like a TL431 won't react nearly quick enough, and can't handle that much current anyway (~100mA; figure ca. 10A peak during an ESD pulse).
TL431 is normally rated for 1mA bias, but that's for VREF within spec. The subthreshold region is poorly documented, but it's usually the case that complete cutoff (Ik <1uA?) comes for V_VREF < 2.2V or so. Which is still a damn sight sharper than any zener diode can do.
Also, if you do opt for an "adjustable shunt" like this, using a high-ohms divider to VREF (assuming IREF is low enough -- TL431 isn't, but one of the low current variants may be, or you can use a CMOS op-amp against a micropower reference to much the same effect), consider putting a capacitor in parallel with the top resistor so that transient changes in output are coupled quickly into REF. Not much should be needed, 1nF would even be a lot.
Also consider using higher voltage zeners (>= 5V) to clamp the brunt of it, then add a series resistor between zener and ADC to limit injected current. A shunt could be used to absorb excess VCC rise, or you can just kind of let it happen and see how bad it is. Most 3.6V (abs. max.) devices break down in the 4.2V range, which may not necessarily be harmful to them, but may disrupt internal state.
I once had swapped out a 3.3V LDO for 5V, which was applied to a PIC24E; it simmered in the 4.2-4.4V range with something like 100 or 200mA flowing. It kinda sorta worked, but it wouldn't always take programming, and the USB device was cacked. Presumably the analog bits (12MHz PLL?) weren't behaving under the... "sweaty" conditions, shall we say. Put in the correct 3.3V LDO and all was fine (no apparent damage to the chip).
Tim
exmadscientist:
--- Quote from: NotAVirus on December 13, 2019, 09:02:01 pm ---I have done some modifications on my initial design. As David Hess suggested, M1 is not required if the impedance on the PNP-base is low enough. This can be done by adding an op-amp buffer between the voltage divider and PNP-base. I have also removed the isolation diode(D3) as this is not needed. When protecting several inputs one could simply add a PNP-transistor to each input, and connect all the base-pins to one single op-amp. Removing one isolation diode should give the circuit a sharper clamping voltage.
--- End quote ---
Note that this circuit does have some appreciable leakage through the transistor's B-E pn junction. If you require very high precision (nA or better), an improvement is to drive the transistor base directly from an op-amp follower buffering the input signal. When the signal voltage goes beyond the op-amp's ability to follow, the transistor will turn on and pull the whole thing down toward ground. No great precision is required of the op-amp, so a series resistor is sufficient to protect its input.
This approach is also viable for bipolar signals, at the expense of added complexity (you'll need complementary transistors and have to avoid transistor reverse mode operation). But it's one of the better ways I've found to protect low-level analog signals when leakage is critical.
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