how to route codec (ADC/DAC), analog pins not all on one side

[loki42]

So I'm attempting to route codec (PCM3168A) and if you look at figure 64 in the data sheet the layout example is rather minimal. The input and output digital interface is on the left and right sides of the chip and the analog input and output are on the top and bottom. This appears to make it almost impossible for me to not cross digital and analog traces. I'm rather worried about introducing digital noise into the inputs and outputs. Should I basically cut around the digital section with the ground plane keep out and then route the one sides digital traces under the component? Then nothing needs to cross the digital / analog plane boundary. My current layout has traces crossing and noise performance isn't near spec. 3.3 and 5 v are coming from separate LDOs, VCOM is buffered and I'm following the data sheet for bypassing.

Are there any layout examples for a similar chip? The example board from TI isn't handy.

[capt bullshot]

Just don't split AGND and DGND, use one solid GND plane for everything (your whole board). Use the series resistors as indicated pg. 51 of the datasheet, these mitigate digital noise. Best placement of them would be at the respective signal source pin. Keep the other digital stuff (as indicated control MCU) slow (e.g. set the pin drivers of the MCU to their slowest working edge drive mode), and / or use series resistors too here. Otherwise, don't mix up analog and digital circuitry in your layout, and don't route digital traces (except the ones required for operation of the codec) through the analog part. Laws of physics take care now to keep the digital noise away from the analog though you don't split the plane.

[loki42]

Sounds good. Is there a way I should route the two i2s signals around the respective analog in and out? Is under the part the right approach or should I cross them?  I.e. the d out and d in are both going to the MCU.

[SiliconWizard]

With a 4-layer board, you could just route the digital signals on the top layer, and the analog on the bottom, or conversely. There would be a solid ground plane (inner layer) between them.

[capt bullshot]

Depends on how many layers your board has. The codec has a thermal pad, so you can't lay any traces on the top layer (I'd recommend against this anyway), and you shall not split the ground plane under the device, so you can't place traces to the layer carrying the plane, so often there's the only choice to route them outside. If you have enough layers, place a GND plane layer between the chip and these traces. I2C is rather slow and often used for initialisation of the codec, so you should have an eye on your software when it uses these lines, preferably keep them quit and in idle (high) state when playing or recording sound.

Edit: Crossing the analog signals with the I2C signals on another layer most probably is the better way than routing the I2C all around the analog part. Avoid looping digital signals around the analog circuitry.

Edit 2: Keep your power supplies to the codec clean. Not the 5V analog only but also the digital 3.3V. Sometimes a seperate linear regulator for these voltages helps, sometimes LC or RC filtering. Be careful with LC filtering, add enough damping to keep it from ringing. If there's a single (or very few) chip digital circuitry with little noisy digital I/O, one might get away with the proper usage of ceramic bypass caps on a common voltage rail.

[loki42]

The 3.3 and 5 v power is from separate LDOs / converters. 2 layer board.  I'm not that worried about the I2C lines but the very high speed and always in use I2S TDM lines.  D out and d in. 

[capt bullshot]

With 2 layers it's very important to have a as solid as possible GND plane, don't slit the plane by traces, I guess this will turn out rather difficult to layout - depends on the complexity of your circuit. At least four layers might be the better choice. A commonly used technique is to pour GND on both sides of the PCB and stitch it with vias to bridge slits in the pours (as a last step of finishing the layout). Before you pour the GND, make sure every GND Pin is connected by as short and as wide as possible traces.
Ideally, the I2S Clk and Data lines operate synchronously to the sampling rate, so their noise gets attenuated by their high frequency nature and the comb filter effect of synchronous sampling. Anyway, the series resistors indicated in the data sheet should mitigate their interference with the analog circuitry. You'd still have to take care of the rest of the digital circuitry to avoid coupling into the analog part, a clumsy placed digital signal, supply or GND trace can ruin your day here as well as not sufficient or ringing decoupling capacitors on the digital side.

Edit: With a 2 layer setup, if well thought, it can be useful to split the GND plane to keep digital (lower frequency) currents away from the analog part. Higher freqency currents are kept away by physics, since their return path follows the trace. Beware, you must not cross the slit with any higher speed signal including supplies, and the codec chip would sit over the connection point of the split plane. You need very careful decoupling of the supplies (make the current path over the split high impedance) to keep noise from coupling over the split.

[loki42]

Here's the current layout for the codec, the current one i'm testing is the same as this but with vias covering the EPAD. I've just removed the TI recommended vias from the EPAD if I want to route through there. So the stuff in the blue box is the digital section of the codec. I've seen confusing advice on if MCLK should be treated as digital. It's very high frequency so I assumed yes.  You can see some of the outs are routed around EPAD. I wanted to check if not crossing the digital lines would help. It doesn't make any difference. The input and output signals are differential.

I'm thinking of routing the right side digital stuff under the part and making the digital stuff surrounded by slots. I'm following the design for terminating resistors. I'm confused if the ones for WCLK and BCLK need to be close to the part though, as I'm routing BCLK and WCLK to both sides of the part from a single terminating resistor.  With the codec on the join approach I'm not sure how to do that with this chip. I'm also confused about how you'd route power in the case.

[capt bullshot]

This layout does look no good to me. First of all, do not route anything between the pads and the thermal pad. Then use the thermal pad as a central GND for the codec chip, route all GND pins directly to the thermal pad. Connect the thermal pad to the GND plane using a convenient amount of vias. Since it's a thermal pad intended to sink some heat, place the vias evenly spaced over the entire area. Place the decoupling caps in a way that both ends of the caps are very shortly (no vias) routed to the corresponding GND and Vxx pins of the codec. Connect the GND ends of the capacitors to the GND plane. Do this as the very first step in your layout. Then route all the signals around the caps, move them slightly if necessary, but do not open the direct connections to GND and Vxx.

Place the analog stuff e.g. west of the codec and the digital stuff east (or any other suitable orientation). There will be some analog or digital lines left that must be routed around the chip, the only way to avoid this would be an at least 4 layer board. If you must route digital lines around the chip, don't split the plane in a way that these traces cross the slit, 90% of the use cases it's better to not split the plane at all. If you place slits in the plane, don't cross the slits with any signal (including Power supply traces and GND / shield of external connectors that might form a loop of any kind). Best way to handle shields of external connectors is to solidly bond them to a solid GND plane.

Anyway, from that small piece of layout show, I'd recommend using a 4 layer board, it's way more easier then to provide the solid GND plane. Still pour  copper GND on the other layers if useful and achievable.

[mengfei]

Nope on that routing.
if your really stucked with 2 layer, you could Fan out, add vias then place some of those SMD's directly below U4
Bypass caps as close as possible to supply pin & shorted gnd return.

Follow the recommended layout of the vendor for better results as they have done a lot of test, trial & error runs on those parts.

[loki42]

Here's the updated routing, I've switched to 4 layers and the ground isn't split. I am a bit confused about what to do with the power plan given all the different voltages I've got. Otherwise if there's any other feedback I'd love to hear it. I'm crossing all the analog differential output signals at one place with the digital signals. I'm still a bit worried about where the digital signals being routed near the 5VA power.

I think I have placed the decoupling caps as suggested but I'm not sure if you mean something else. If there's any other advice on getting closer to the full performance (though I know 24 bit is tough!) of the codec I'd love to know.

[mrjoda]

Hi,

avoid the acute angles, it's called Acid traps (google some PCB layout guidelines). I do not like the routing of 3V3VA to oscillator. I would not share one capacitor and one trace with power pad of chip.  Otherwise it looks better than in previous case.

There are many other things that should be improved, like grounding vias for example, loop reducing and etc. 

[loki42]

I'm not sure what you mean by the 3V3VA to oscillator, there are 3 caps there. I've made the power traces planes on a separate layer though I'm not sure if that's a good idea as the multiple different power planes will be over a single ground plane. Not sure if that's better or worse than just running traces.

[SiliconWizard]

There are a bit too many vias in this thermal pad IMO. This could cause definite soldering issues, unless the vias are plugged, which would be costly and unnecessary here. Just a thought. A thermal pad is not swiss cheese either.

[loki42]

That's just the default footprint from TI. I'll reduce the number.  Their paste layer is a bit weird too.  The recommend just one big aperture. 

Any advice on the 3.3 / 5v / 5v analog power planes?  Should I run the split power planes or use traces?

[capt bullshot]

If there's more than 2 or 3 power rails that you can't divide into planes with a few simple sketches, I do prefer to run traces as wide and as short as possible, then pour copper of the respective potential around the traces, with the result similar to planes (little non-copper area left). Your component placement should keep the components running off a particular rail together, so in the end result it'll look like a split power plane. Keep the goal in your mind: GND and supply distribution shall be low impedance.

Regarding the thermal pad paste: One big aperture may work, often an array of 4 to 9 equally spaced apertures is used to improve production yield - ask your EMS for best results and experience.

[thm_w]

Routing looks so much better now.

Hi,

avoid the acute angles, it's called Acid traps (google some PCB layout guidelines). I do not like the routing of 3V3VA to oscillator. I would not share one capacitor and one trace with power pad of chip.  Otherwise it looks better than in previous case.

Doesn't matter.
For the 3v3, there are three caps in that area, probably not ideal but will work.
Although if that purple line is the 3v3 power trace going off, I would fatten that a bit, no reason to have power trace so thin.

[loki42]

Do you mean the acid traps stuff doesn't matter? I've seen a few people say it hasn't  been an issue for a decade or two.

What would be ideal for the 3v3 cap wise?  Oh and there are planes where ever there are power traces so I've made that trace big now to make that more obvious, as @capt bullshot suggested.

I'm not sure if I need to use anything more snazzy than an LM358 to buffer VCOM. I given it's buffering the reference any noise in there will couple directly but I'm not sure if the level with no gain is an issue.

[mengfei]

what's with the weird traces? like those below U4 which should have all been straight?
what software are you using? if possible get supply directly from the supply line like the last output cap & not share all on a single rail "IF" possible
acid traps are corners where chemicals can be well trapped 

your lucky you can work with multi layer boards while I'm still doing single side boards for SMPS, PTH + SMD's

[loki42]

The ones under U4 just become the ground plane, if you look at the image with the planes.

[mengfei]

The ones under U4 just become the ground plane, if you look at the image with the planes.

I meant the traces going inside U4 pins, why are they crooked? & some other  traces have weird routing too, did you use auto route?
   

[loki42]

no but I did use the push / shove router and did move a few things. Is there any performance issue with this or is it aesthetic?

Should I look for a buffer with lower noise than the LM358 or will it be low enough to not be an issue buffering VCOM.  Should I worry about low frequency return paths passing under the oscillator? 

[capt bullshot]

I'm not sure if I need to use anything more snazzy than an LM358 to buffer VCOM. I given it's buffering the reference any noise in there will couple directly but I'm not sure if the level with no gain is an issue.

Depends on your circuit. If VCOM isn't loaded (e.g. used like the example circuits), you don't need a buffer at all. If VCOM is loaded by anything that can cause current flowing into and out of the LM358 (any kind of AC), the result will be terrible. If you have a nice and steady DC load, you might get away with proper filtering.

The crooking mentioned is an aesthetic issue and surely has no impact on the performance.

Acid traps shouldn't be an issue with a modern fabricated PCB. Anyway, I do avoid acute angles, crooking etc. since it makes the layout look ugly to an experienced eye and it'll easily get judged as a pointless beginners work that wouldn't work anyway. If you do it for your own and don't showcase it and it works, aesthetics don't matter.

[loki42]

I'm not sure how much load is unloaded, they are used to bias the op amps through 1 M resistors. It'll be around 25 uA total. I could get rid of that by switching to dual supplies.

[capt bullshot]

1M resistors in the analog signal path isn't particular low noise anyway ... Biasing a "+" input of an OPAMP could be considered "no load", depends on the OPAMP, but the bias node itself would still have to be low impedance for AC. Your issue might not only be layout related.