Wait. Did this guy just solve the MOS feature size limit?
If such diode-based logic is synthesizable, Schottky barriers and small inductors can be printed using the usual CMOS photolithography process and the circuit have a manageable power draw, we may be able to build CPU chips with a minimum frequency requirement of a few GHz at a feature size of single-digit nanometers with DDL internals.
"Introducing Intel Core i7-9770K hexa-core mainstream performance processor with 4nm DDL process, and a base clock of 7GHz and boost clock of 7.5GHz. It can mostly be overclocked to over 10GHz easily." 
Hmm, interesting thought.
I don't think it's possible, though. AFAIK, it depends on reverse recovery, which will take some um of height and width, and distance and/or isolation trenches between diodes. It's also a lossy process, so it might have similar process and thermal limitations to the last runs of NMOS.
And with detectors and filters, I don't think it would be very amenable to high clock rates, though that is something that can be controlled at least: I'd suppose 1N4001s could be replaced with 1N914s (or even smaller and faster PN diodes), and 1N914s replaced with RF schottkys, using an excitation source of a few GHz, and a usable logic rate on the order of some 100s MHz.
Personally, I look forward to ~10nm lossless CMOS: the chip is biphase clocked, with nice smooth sine waves or whatever, and there's a data input, data output, and an "entropy dump". (The "dump" is necessary, because all computations must be reversible, e.g., using Toffoli or Fredkin gates. Eventually, some unwanted data must be discarded, making the computation irreversible; hence, "entropy dump".) This would also be the perfect design lead-in to full quantum computing, which is also reversible.
Since it's lossless, there's no need for a supply rail, and the clock lines look largely capacitive. (The gates effectively connect or disconnect data lines from the clock lines, so voltage transitions are always carried by the clocks.) Losses arise from the usual sources, but also any irreversible calculations. The clock lines therefore look like lossy capacitors, so you'd use a resonant supply to power the circuit. The entropy dump might just be some resistors. (It shouldn't be possible to recycle the "entropy" energy, but maybe it's okay to use some diodes to get some back.)
The important feature being, though the logic is bigger (you're passing more signals in and out of each gate, and the gates need more transistors), you can integrate it as high as you want, with little concern for overheating. This, of course, depends critically on having some efficient way to grow stacked circuits, which simply doesn't exist right now...
Tim
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