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| IC advice to create a regolable oscillator from 0 to 500kHz |
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| ogden:
--- Quote from: imo on April 02, 2019, 05:00:27 pm ---The 9833's "MSB" is with 28bit resolution. Therefore the square wave too. It is the same situation as with the 9851 and its comparator. --- End quote --- Yes you are so right. My bad :P It is output jitter up-to 1/FCLK for 9833 that differs between two. |
| stockvu:
--- Quote ---Square wave output of this DDS is just MSB of the DAC - far from DDS resolution. AD9851 have built-in comparator for proper square wave output, yet it is huge overkill for 0..500KHz application. --- End quote --- Hi. Well, I don't think the OP specified things like jitter or settling time -- but I may have missed it. I don't have a Jitter Test Set or a Spectrum Analyzer to evaluate these 9833 circuits. On my low cost scope, the outputs seem stable and agree well with freq counter. I run one DDS 100x higher in frequency and then pipe it into the 2560 Timer-5 input. There its divided by 100 and T5's Output-Compare generates selectable duty cycle from 5-95% (no comparator needed). An added benefit is 0.1 Hz resolution now becomes .001 Hz. So I admit its overkill -- but I like overkill when its cheap. :) |
| ogden:
--- Quote from: stockvu on April 03, 2019, 03:28:14 am ---Hi. Well, I don't think the OP specified things like jitter or settling time -- but I may have missed it. --- End quote --- He did not. Knowledge may be useful for others who read this. --- Quote ---I don't have a Jitter Test Set or a Spectrum Analyzer to evaluate these 9833 circuits. On my low cost scope, the outputs seem stable and agree well with freq counter. --- End quote --- It is hard to notice on low output frequencies. FCLK/4 have no jitter but FCLK/2.5 is worst case. Look at > 4 periods on scope and you will see. BTW you don't even have to put DDS into MSB mode - just look at DDS DAC output w/o LP filter at FCLK/2.5. It will be eye-opening on itself. Then you start to realize how critical is output low pass filter especially for high freq output of DDS, why sometimes it is designed to be steep 7-th order or even better, filter. Disclaimer: all noninteger (relating to FCLK) frequencies have this behavior, FCLK/2.5 was just simple worst case pick. [edit] Ups. I talk about non-integer divisors, yet use round number, 3 :palm: Fixed to FCLK/2.5 |
| stockvu:
--- Quote ---It is hard to notice on low output frequencies. FCLK/4 have no jitter but FCLK/3 is worst case. Look at > 4 periods on scope and you will see. --- Quote --- --- End quote --- BTW you don't even have to put DDS into MSB mode - just look at DDS DAC output w/o LP filter at FCLK/3. It will be eye-opening on itself. --- End quote --- I take output off the DAC MSB. I don't need the triangle or sine outputs. My use of this circuitry never sees an RF channel, it doesn't get low-passed since it feeds digital chips downstream. Thanks for the tip on looking >4 periods, that's good to know. If I do have some jitter, its not a problem for my application. I just threw in the DDS idea as another option for the OP to consider. |
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