For bandwidths up to a few MHz it may be better to build a real time digitizer using Cypress FX2 and an 8-bit parallel output ADC.
Alternatively, implement a complete scope on some MCU with built-in fast ADC. This has already been done.
Sampling scopes make sense at bandwidths faster than any ADC you are willing to pay for.
Also, to the OP, if you want to connect something to your computer, you better have good input overvoltage protection

Here is the same idea but with 1 GHz bandwidth:
https://www.electronicdesign.com/boards/1-ghz-sampling-oscilloscope-front-end-easily-modified
I have seen this article a while ago while researching high speed sample and hold solutions.
I think there are certain problems with it which the author glosses over a bit.
the master bridge is loaded with only a low-input capacitance of about 1 pF. Because the bridge’s on-resistance is about 100 Ω, the RC time constant is around 100 ps.
I'm not sure if that's accurate, I think it should be added to the 50Ω impedance of the cable, giving τ=150ps.
The actual sampling event happens in the track-to-hold transition. It takes place during the few hundred picoseconds in which the master Schottkydiode bridge resistance switches from low to high. Such switching occurs within a small, central part of the full 8-V applied step.
And here's the first problem: if sampling time isn't long enough for the capacitor to fully settle, its state will be measurably dependent on waveform preceding the sample, because the gate is ON for a very long time before taking the sample.
Notably, I would expect a step response similar to trace B in the article. For sampling time of 300ps (1GHz BW), which is merely 2·τ, the initial step would reach 90% of full scale and then exponentially decay towards 100%. I don't know if adding speedup capacitor is a legitimate solution.
The author blames his poor step response on cable attenuation. RG58 is rated about 50dB/100m at 1GHz, so 4dB/8m, so about 1.6x attenuation. That's in line with what we see so the author can be excused.
But I think the cable only adds to the error described above, and the error above would remain if a higher quality and shorter cable is used.
There is probably a reason why Tektronix made efforts to produce very short pulses rather than just fast-falling pulses in their S-1/S-2 sampling heads.
Though OTOH their diodes probably had much higher dynamic resistance - given that the sample signal needed to be amplified 40x, sampling time must have been a short fraction of τ.
These days a long, fast-falling pulse would perhaps suffice, but only with some really low resistance diodes (I think I have seen down to 30Ω) and perhaps smaller sampling capacitance.
I wonder if it would be feasible to use a tiny capacitor directly between the sampling gate and ground, and a noncapacitive resistor branching-off to the buffer amp, such that only the small cap needs to be charged during those short picoseconds. The buffer amp would compensate for the loss caused by distributing charge from the sampling cap to other capacitances in the system.
Another advantage of that approach is that it doesn't put the guts of a low speed JFET opamp in a wideband signal path. Who knows what's the frequency response of parasitic capacitance of TL-072 input pin and the supply bypass capacitors in series with it

Another problem with TL-072 is it dependence of capacitance on common mode voltage. Ideally, it should run on as high voltage supply as possible and/or be replaced with something better-behaved. OPA1642 supposedly is good.