I don't think extreamly low leakage transistors are required since the input signal is permanent, meaning the hold time should be enough to mantain an stable output at low frequecy's and not much more since it will always be charging with the next peak of the input signal.
I would use an AD8307. Works from DC to 500MHz. You get the LOG(input_peak_value) at the output (0-2.5V output).
https://www.analog.com/media/en/technical-documentation/data-sheets/AD8307.pdf
I found abaout it in other post but it scapes my knowledge of how i should implement it, also it's expensive and where i live they don´t sell it. If i can't make this work i will look at it again and maybe i can get it shipped in a reasonable time, here customs take from two to five moths if you are a normal buyer like me.
To OP: What is the arm chip? If it has an ADC, may be you don't need peak detector after all, sampling input fast enough by 12-bits ADC and running peak detector in software.
Well... you're right. The OP talks about 500kHz max. Many recent MCUs have several-MSPS 12-bit ADCs, so that should be doable in software without much problem.
Now if a 12-bit ADC would not have enough resolution for the OP's needs, then I think they would be dreaming if they think they can get better than the equivalent of 12-bit with a simple, fast and pure analog peak detector...
That was my first thought, sadly, analog implementation is as must, teacher's requirement

. We are using an F103C8T6 which has a 14Mhz ADC.. More than enouth to sample a 500Khz signal. If this gets too difficult maybe i can persuade him haha.
The version I know of the simple 2 OP circuit uses an additional diode in feedback for the 1 st. OP, so that the OP only has to slew some 1.4 V when a new maximum is detected.
For long hold times, one can combine 2 such circuits in series.: a fast one with a rather small hold capacitor and a slower one to extend the hold time.
The fast part should than have a defined drift direction down.
The transistor circuits look good.
I tryed that technique, however, the problem here is the op not able to deliver the necesary current to charge the cap at high frequencies, so the primary diode gets replaced by the base-emiter junction of a bjt.
Replacing the diode with a transistor allows charging the hold capacitor with a much higher current without lowering the value of the pull-up resistance which applies to your existing circuit.
In case I was not clear enough about this, replace your diode D2 with a transistor with its collector tied to the positive supply. Now the current available from R7 is multiplied by the transistor's current gain to charge the hold capacitor faster. The example I gave uses the same idea.
The reverse breakdown voltage of the base-emitter junction will limit the maximum range of operation to about 5 volts peak-to-peak however. If this is a problem, then a diode placed in series with the base can be added.
Thank you for the clarification, i tryed this approach and found it works really well.... But (there is always a but

) i have some doubts about the circuit i came up with. Replacing both diodes with bjt's works, however, now at low input voltages (1V) the diference in voltage between the inputs and the feedbak from the output needs to be almost 100mV higher for the LM393 to stop charging the cap and there is always a 50 to 80 mV diference in charged value at 5v, i can live with that even though it's higher than 2% error. Here is the circuit:

And here the simulated results, first at 1kHz and 1V peak, then 400kHz and 1V peak, finally 400kHz and 5V peak value.



Once again thank you all for the replys