EEVblog® Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: ricko_uk on January 05, 2025, 06:08:56 pm
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Hi,
I have a hierarchical design with 6 channels as shown in the attached screenshot. Some nets like the RS485 are all joined together across all channels. Some nets like the HNDSHK_B are all independent (i.e. not connected across channels).
For some reason I get hundreds of errors for several nets like the uC_IO_HNDSHK_B. This is an example:
Nets Element[0]: uC_IO_HNDSHK_B1 has multiple names (Net Label uC_IO_HNDSHK_B1, Net Label uC_IO_HNDSHK_B1, Net Label uC_IO_HNDSHK_B1 (Inferred), Net Label uC_IO_HNDSHK_B_EDGE1, Net Label uC_IO_HNDSHK_B_EDGE1)
For example, looking at net uC_IO_HNDSHK_B it looks like it generates uC_IO_HNDSHK_B1 and uC_IO_HNDSHK_B_EDGE1. Where "EDGE" is the repeated sheet name.
Any idea why am I getting that error?
Does anybody have any suggestions?
Thank you!
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This is common to get when repeating a schematic block. There is one TOP_LEVEL_NAME outside of the block, that is linked to a net named TOP_LEVEL_NAME_CHANNEL# inside the repeated blocks.
The fix
Place a No ERC (Place>Directive>Generic No ERC) on error nets outside of the repeated block.
Double click on the ERC to change the settings from the default All violations, instead select something more useful. There is an option to suppress the issue with multiple names in the bottom section.
Pictures and more info here:
https://www.altium.com/documentation/altium-designer/design-validation#controlling-the-printing-of-no-erc-directives (https://www.altium.com/documentation/altium-designer/design-validation#controlling-the-printing-of-no-erc-directives)
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Better post in the Altium forum, I think.