Infineon's low-frequency CoolMOS S7 what is the difference from "fast" MOSFETs?

[Miyuki]

Hi folks,
I have a question. How do they make a "slow" S7 MOSFET when all parameters, like gate charges and capacitances, are almost the same as in a "fast" P7 line.
Is the modern complicated super-junction transistor not characterized by its parasitic changes/capacitances?
Because when I look at the datasheet of two devices with the same Rds their Qgx are +-10% and the same apply for capacitances
The only big difference I see in the parameters is dv/dt ruggedness 20 vs 80 V/ns and Reverse diode dv/dt multiple times better
And better RthJC for the "slow" device
Comparing for example IPP60R022S7 and IPW60R024P7
They even stand: "above 20 kHz the advantages of CoolMOS™ S7 gradually diminish"
I can see, that in the fast boost stage, 20 V/ns can be a limiting factor, but otherwise, I can't see any clear problem.

[T3sl4co1l]

Links:
https://www.infineon.com/dgdl/Infineon-IPP60R022S7-DataSheet-v02_01-EN.pdf?fileId=5546d4626bb628d7016bc25d1085779d
https://www.infineon.com/dgdl/Infineon-IPW60R024P7-DS-v02_00-EN.pdf?fileId=5546d462696dbf120169b48730044ab3

Three things, I would guess:

1. dV/dt is a rating determined by how the junctions/layers are interconnected.  For the MOSFET, turning on the parasitic BJT (drain-substrate-source) must be avoided, which can occur by capacitive coupling.  The B-E junction of this BJT is effectively shorted out by a finite resistance (source/body spreading resistance), thus an RC differentiator is created, and a critical rising dV/dt can turn it on.

2. Diode dV/dt is the same effect, exacerbated by the residual free charges from body diode conduction (minority carriers).  As charges clear the junction and it becomes depleted, the width of the depletion region -- thus its breakdown voltage -- gradually increases.  In rectifiers, this is observed directly as the dV/dt slope (and corresponding turn-off losses) in inductive commutation.  In MOSFETs, the free charges make the parasitic BJT more sensitive and thus the dV/dt limit is lower.

In either case, BJT turn-on incurs additional minority carriers, which take time to dissipate (like a diode reverse-recovery tail, or IGBT turn-off), and which can result in unstable current flow -- rapid breakdown and destruction.  The breakdown mechanism is the same one which allows small BJTs to act as pulse generators, but which only occurs at a single point (as far as I know) -- thus the entire junction capacitance of the device (plus any attached load, eventually*) discharges through a, perhaps nanometer sized point, quickly turning it into a crater.

*Since it'll take many nanoseconds for any load current to begin flowing to this magnitude, due to lead inductance.

The same effect applies to avalanche breakdown, and indeed we see this device has quite a low rating: I_AS = 3.8A, compared with 12.2A of the P7.  (Which still isn't all that much, considering an older device like IRFPS43N50K -- granted it has probably twice the die area, given the about double E_AS and Qg(tot) -- is rated for full load current at avalanche; beefy!)

Curiously, they claim a 9ns rise/fall time at 300V (inductive load) for the part, or 33kV/us.  I'm not sure what distinction (if any) should be made, or is meaningful, for self-commutated versus externally-commutated operation.  It does seem rather suspicious.

For more detail on dV/dt, see: https://www.mouser.com/pdfdocs/Impacts_of_dv-dt_Rate.pdf

3. The SuperJunction structure itself has capacitive losses.  Perhaps this has been optimized as well for the device?  I don't know how fine they're making these structures these days.  It doesn't seem to have improved this much between the two, you're right.

SJ is... weird.  I wrote this post a little back, https://www.eevblog.com/forum/projects/superjunction-pulse-generator-(of-sorts)/msg4767362/#msg4767362
apparently it can be so abrupt as to generate very sharp risetimes in otherwise innocuous (i.e. dis/charging with a large-value resistor) conditions, hence the headline figure in the post.  It has a dielectric loss effect, which can be understood as the bulk resistance of the N/P pillars working in series with their capacitance, and so when the structure changes from fully depleted (high Vds, very low capacitance) to partially (low Vds, very high capacitance), charge has to rush in along those narrow pillars, acting in series with the sudden change in capacitance.  At high frequencies (100s kHz), it manifests as dielectric loss.

Tim

[Weston]

You are probably not going to get a full answer unless you talk to an Infineon apps engineer, but from the product literature for the S7 series:

"By focusing on applications where switching losses are not relevant, the CoolMOS™ S7 SJ MOSFET is stripped off the features related to switching performance and therefore has an optimized cost positioning, while reaching very low RDS(on) values. The CoolMOS™ S7 MOSFET is built on a successful technical optimization of Infineon’s CoolMOS™ 7 technology that removes from the device redundant features, related to switching performance, as they are not needed in low-frequency switching applications."

You are probably not going to see a price difference with the distributor pricing, but it sounds like the S7 parts are stripped down to achieve a lower cost when you buy in volume. The optimizations must either allow for a lower on resistance per die area, or allow for processing steps during fabrication to be skipped/reduced (different doping, or reduced interconnect, etc).

As T3sl4co1l discusses, it seems like the devices are more vulnerable to latch up as a consequence of that. Or the Coss could be more lossy, they don't specify that in datasheets.

[T3sl4co1l]

I'm curious what the optimizations actually are, because it doesn't seem like die area is much reduced; the package is smaller, but considering charge and power are similar (power is actually slightly higher, despite the smaller package....if you believe their number!), it can't be by much, if at all.

Also besides the shorter rise/fall times, RG is lower, which is... weird?

I almost wonder if it's secretly a banger, if they optimized it for better switching loss while turning down the robustness.  I mean, I avoid avalanche whenever possible in my designs, and, perhaps with the uptake of GaN, designers will be better aware of robustness issues, avoiding breakdown.  Meh; probably given the priority for dV/dt, some avalanche robustness is inevitable?

Tim

[Miyuki]

Might it be some wafer-thinning technique? As avoiding some layers and grinding it down?
Like are there some extra layers that add the required thickness and affect robustness?
Because the slow one has RthJC 0.32 and the fast one 0.43 with probably a similar die area because the capacitances are the same.

[jbb]

I suspect they said “stuff it” and ignored (almost ?) all reverse recovery constraints while optimising the device cell. That could well open up opportunities for different doping regimes.

Maaaaybe if they’re not after switching performance it might be possible to relax constraints on (linear mode) gate threshold and transconductance.

But I’m not a semiconductor engineer so those are just guesses, really.

[T3sl4co1l]

SOAs are very similar too; 2nd breakdown over almost the whole plot, with a similar breakpoint.

Tim

[JohnG]

Short answer: The "effective" internal Rg is bigger, so the device switches more slowly.

The data sheet internal Rg is a bogus number, because the real Rg is a distributed resistance. If you measure the Zin vs frequency, you will not get a nice, single-pole RC response. A test at 1 MHz (the standard test) does not tell you a lot about the switching when the actual gate drive transition times are on the order of ns to a few 10s of ns.

Some time ago I was in attendance at a discussion given by engineers from Infineon. It turned out that a significant number of power supply designers had real problems with the speed of CoolMOS (severe ringing, EMI, etc.). If you have been in the business for a while, this should not be a surprise, though it is still sad. According to my (imperfect) memory of the discussion, it became simpler to develop a slower part. Then, if a customer could not learn to deal with the faster devices with high potential for both performance and problems, you could just recommend the slower part. Easy peasy, EMI drops, ringing gets better, no other circuit changes needed.

This actually makes a lot of business sense, because if you have a bad design, and the factory line is built and the product delayed because it can't pass emissions, the last thing your boss is  worried about is efficiency.

John

[T3sl4co1l]

"Bogus" would be overstating it.  It's not a single resistance, sure, but it's the effective resistance measured at the pin: the ESR of the gate capacitance.

In earlier times, gate and source were simply huge blobs of metalization; well, gate as a mesh, since source connects through it with vias, but yeah.  Gate spreading resistance was just that: the resistance from spreading through that resistive plane.  Such parts typically have a gm ~ 1/sqrt(F) asymptote, rather than a hard fT cutoff (as a dominant pole RC would give).

Modern parts, AFAIK, are designed in such a way as to give a single dominant pole.  This maximizes baseband bandwidth (that is to say: switching rise/fall time).  It might be done by fractal interconnect for example.  (Gate pad connects to a wide strip spanning most of the die, off which many thinner strips connect; off which many many more, even finer, strips connect; etc. Probably only 2-3 levels of this are necessary to maximize a typical design.)

Despite their tendency to oscillate at obscene frequencies (I've seen ~400MHz before), the RF performance is quite poor -- while gain remains high (enough to oscillate, anyway), the available power drops further and further, hence those ~400MHz squirrelies are basically useless as anything other than an EFI nuisance; you're not going to be making a power amp that way.  Which is more or less in line with expectations.

At least, the last few I measured RG on, this seemed to be the case.

I don't have any particular reason to doubt the reported RG of the present device, and it is inline with the fast switching speed.  I am quite curious though, if those figures together are actually real or what.

Tim

[JohnG]

It has been some time, but in an earlier job, I had measured quite a few MOSFETs and for most, the impedance curve from gate to source was quite a bit softer than a textbook single-zero (after removing the effects of Cgd as best as possible). Did a lot of testing under a variety of conditions. If I recall correctly the fastest CoolMOS were better than most. Unfortunately, I don't have the data or the notes anymore, they got left behind with the job.

For most people, this doesn't matter that much, because it's in the noise. Where it matters is when you are trying to turn the whole FET completely on in a few ns, but this is an uncommon need.

Superjunction parts have some other gotchas, like atrociously high Qoss and the almost step-like change in Coss and Cgd with V. People complain about GaN and EMI, but superjunction parts can show a crazy fast voltage rise during turn-off. And yet, they are great parts for a lot of applications if you learn how to use them.

John

[T3sl4co1l]

Even when driven passively, it seems:
https://www.eevblog.com/forum/projects/superjunction-pulse-generator-(of-sorts)/msg4767362/#msg4767362

They also have dielectric loss, of a sort:
https://www.eevblog.com/forum/projects/proof-mosfet-datasheets-lie-to-you!/msg4756709/#msg4756709
making them a lot less advantageous in resonant applications compared to square-pulse type -- that is, the difference is smaller than the pulse/resonant difference for non-SJ types was.

Tim

[T3sl4co1l]

Oh yeah, this is relevant, I had done a step response of FQA9N90C about five years ago:
https://www.seventransistorlabs.com/Images/FQA9N90C_Gate_TDR.png
I don't remember where the source data came from (this predates my GPIB adapter, so, maybe it was by photo and painstaking curve fitting??), or what the setup was exactly.  Might've been breadboarded, with D shorted to S, which would be easy enough.

(...Ahh there it is, found it. Blurry photo, must be curve-fitted, yup.  What a dark time it was... )

(...Ahh, and here's context: https://groups.google.com/g/sci.electronics.design/c/TCNlRsP21Uo/m/z96tG6uLEwAJ Groups are no longer searched by Google, you have to go and look specifically there.)

Ah, or probably inline.  Think it must've been: signal generator --> cable to scope --> tee to BNC-binding posts --> short twisted pair to G-S; D-S shorted.  The high frequency mode being CM of this whole thing flapping around, so, easily written off as irrelevant.

Anyway, the model fit I think came close enough as an RC, and that's about it?

Have seen another TDR-style measurement with similar results.  Again, don't know if that's because of difference in metallization thickness or topology or what, or how often it's used these days, but it seems a welcome difference to older types.

Tim