I have spent the last few days tracking down a frustrating problem with an FPGA SPI interface. The FPGA is the slave and a level shifter is used to shift up the 1.8V MISO signal to the 3.3V MCU domain.
I was unable to determine why in some cases bytes of all zero would be read, and why some bit patterns (but not all) were received incorrectly. I thought it was a defect with the design of the SPI IP inside the FPGA. However the mystery was revealed when I tested the input and output of the MISO channel of the level shifter (the other direction of channels are shifted by another device.)
The output has become very "latent" and is prone to noise, so much so that it was occasionally shifting bits into the next bit position at just 6MHz. The part is rated to ~6ns input-to-output delay in this configuration so should be capable of >50MHz data transfer without error. I originally suspected I might have mucked up and not connected the /OE or DIR pins, but I double checked these and resoldered the entire part with no change to its behaviour. Sometimes, the part would fail to work altogether, and other times I'd get erroneous transitions causing a "double edge" SPI data bit, which was particularly odd.
Replacing the part fixed the issue. Parts were bought from Mouser.
Has anyone else seen this failure before?
In the below scope screenshots, dark blue is output, pink is input, and yellow is the SPI clock.