Is it OK to directly tie logic inputs to Vdd?

[741]

Typically, generally that is, when a pin is meant to be always at logic 1.

Just now, I have a long route to Vdd on a Veroboard PIC design. I could have gone directly "through" an un-used pin (these default to input). In the attached image, is it safe to wire pin RA7 to Vdd? Is it "better=safer" to always use say a 1k, 10k etc (even if the pin is meant to always be at logic 1)?

[T3sl4co1l]

As long as the port initializes in Hi-Z, weak pull-up/down, or logic-high state, and is never changed to a state other than those, yes.

Tim

[MarkF]

In the good old days, tying a pin directly to Vdd would cause problems with TTL logic.
I do not know how necessary it still is today.
I always go through a resistor for a 'high' logic state. More out of habit I suppose.

[Ian.M]

Its almost always safe to tie a CMOS *INPUT* direct to either supply rail.  Its *NOT* safe to tie old bipolar true TTL inputs direct to Vcc as glitches on Vcc could cause latchup and destroy the chip. 

However tying MCU I/Os direct to a rail is strongly frowned upon.  You may see it in cost-minimised high volume products, but all it takes is for the port output latch to be in the opposite state then for a glitch^* or software bug to make the pin an output and there is a high risk of device damage or destruction.   The minimal cost solution to unused I/Os is to set them as outputs and set them low.

Veroboard implies a prototype so active software development with a high risk of bugs.  If the PIC is socketed,  crop that pin of the socket so you can use the track for power.   If not, isolate its pad and use a jumper for the power rail, track side if you have to.

* e.g. a bit-flip due to a cosmic ray cascade, even though such events are extremely rare at sea level, or due to a power transient.

[SiliconWizard]

Its almost always safe to tie a CMOS *INPUT* direct to either supply rail.  Its *NOT* safe to tie old bipolar true TTL inputs direct to Vcc as glitches on Vcc could cause latchup and destroy the chip. 

Oh yeah, I remember that.

However tying MCU I/Os direct to a rail is strongly frowned upon.  You may see it in cost-minimised high volume products, but all it takes is for the port output latch to be in the opposite state then for a glitch^* or software bug to make the pin an output and there is a high risk of device damage or destruction.   The minimal cost solution to unused I/Os is to set them as outputs and set them low.

I agree with this. I personally don't do it, especially with software-configurable pins, way to dangerous. A way to kill your device due to a stupid bug, no thanks!

There's also the slight possibility that said pin would get "zapped" for any reason during the lifetime of the product (eg: ESD), thus possibly shorting the power supply. Whether this is an acceptable failure mode is up to you, but it may not be.

So yes: if we're talking about typical GPIOs - just set unused ones as outputs, and you're done. If there's a software bug and some of them would not be set as outputs, the only thing you'll get is an increased power consumption, not a kill of your device. On some MCUs, you can also disable the GPIO entirely - it gets powered off - instead.

Now if some pin REALLY requires to be "tied" to Vdd, I'll use a series resistor to limit any potential damage, but as said above, the cases where it's really *required* are usually a few, so that adds almost no cost or PCB area.

[free_electron]

Its almost always safe to tie a CMOS *INPUT* direct to either supply rail.  Its *NOT* safe to tie old bipolar true TTL inputs direct to Vcc as glitches on Vcc could cause latchup and destroy the chip. 

Can someone explain why ? This is illogical as True TTL "inputs" are actually the emitters of the input transistor.  They are actually outputs . that is why in the TTL world you have to deal with 'fan-out'. the ability of an output to drive a number of inputs. When pulling an input low you are pulling current out of it. When setting a TTL input high no current flows as the base-emitter junction is now non-conductive.

So tying an unused ttl input hard high is perfectly safe. Nothing will happen.

[langwadt]

As long as the port initializes in Hi-Z, weak pull-up/down, or logic-high state, and is never changed to a state other than those, yes.

Tim

I seem to remember seeing recommendations for sometimes tying unused pins on FPGAs to GND/VCC and setting them as output to get more "power pins"

[Yansi]

Its almost always safe to tie a CMOS *INPUT* direct to either supply rail.  Its *NOT* safe to tie old bipolar true TTL inputs direct to Vcc as glitches on Vcc could cause latchup and destroy the chip. 

Can someone explain why ? This is illogical as True TTL "inputs" are actually the emitters of the input transistor.  They are actually outputs . that is why in the TTL world you have to deal with 'fan-out'. the ability of an output to drive a number of inputs. When pulling an input low you are pulling current out of it. When setting a TTL input high no current flows as the base-emitter junction is now non-conductive.

So tying an unused ttl input hard high is perfectly safe. Nothing will happen.

I've beend also told at the college from one of the professors, that tying TTL inputs directly high is not permissible. Tried to argue the same as you are writing, never succeeded. Neither did I get any further explanation.

[edavid]

Its almost always safe to tie a CMOS *INPUT* direct to either supply rail.  Its *NOT* safe to tie old bipolar true TTL inputs direct to Vcc as glitches on Vcc could cause latchup and destroy the chip. 

Can someone explain why ? This is illogical as True TTL "inputs" are actually the emitters of the input transistor.  They are actually outputs . that is why in the TTL world you have to deal with 'fan-out'. the ability of an output to drive a number of inputs. When pulling an input low you are pulling current out of it. When setting a TTL input high no current flows as the base-emitter junction is now non-conductive.

It's because in original TTL, the absolute maximum input voltage spec was 5.5V, while the absolute maximum V_CC spec was 7V.  So if your V_CC went above 5.5V, the input BE junction could conduct (zener), degrading the input transistor.

74LS has DTL inputs with a maximum input voltage spec of 7V, so this issue went away.

As far as I know, latchup is not possible in a TTL process, since there is no PNPN structure.

[Ian.M]

Its over 30 years since the inventor of TTL logic died and 55 years since its commercial introduction.  The odds are against even a  tea-boy from the original design lab still being alive and compos-mentis.  Original data books and technical briefs were exclusively in 'dead tree' format, are now rare, and if preserved onllne are almost invariably poorly indexed and usually not text searchable, making it difficult to locate the root cause behind any particular common practice.

Therefore unless an experienced bipolar IC designer with access to the original 7400 series TTL masks, who has  considered all possible parasitic structures of a multiple emitter TTL input, including lateral ones, and the possible effects of Zenering the E-B junction or isolation junctions associated with the inputs and is willing to chip in on this discussion tells me otherwise,  in the rare event that I am using 'real'  multiple emitter TTL, not Schottky DTL pretending to be a TTL family, I'll continue with the accepted industry practice of that era of using a 1K pullup resistor when tying an input high, *EVEN* *THOUGH* I don't have details of the exact failure mode that practice was ment to prevent.

[artag]

In boards consisting of many common SSI and MSI parts, production test could be done by in-circuit testers which would exercise the parts using library tests. Tying an input high or low made those library tests unusable so they had to be modified -- at a cost of time and test coverage - to use only the available pins. Feedback (eg a latch configured as a counter such that an output pin change could affect an input) was also a problem.

I doubt that many tests are performed with that sort of equipment these days. Functional testers which test the circuit functionality as designed rather the components as specified are harder to program but may be faster. Self tests can give partial coverage. FPGAs and other programmable devices don't have library definitions. So these restrictions are less important than they once were, but design for manuacturing is still important and thought should be given to test and repair when the circuit is designed.
   

[mzzj]

http://www.ti.com/lit/an/sdya009c/sdya009c.pdf

if a high level is required, it should be connected with a voltage source corresponding with a
high level. In general, this is the positive supply voltage VCC. Figure 10 shows how, in the previously mentioned cases, a fixed
potential should be connected to unused inputs. Note that a high level should be applied to the unused inputs of an AND
(NAND) function and a low level to unused inputs of an OR (NOR) function.

Devices with multiple-emitter inputs (SN74 and SN74S series) are exceptions. Since no voltage greater than 5.5 V should be
applied to the inputs (because if exceeded, the base-emitter junction at the inputs breaks down), the inputs of these devices must
be connected to the supply voltage VCC via series resistor RS (see Figure 11). This resistor should be dimensioned such that
the current flowing into the gate or gates, which results from overvoltage, does not exceed 1 mA. But, because the high-level
input current of the circuits connected to the gate flows through this resistor, the resistor should be dimensioned so that the
voltage drop across it still allows the required high level. Equations 1 and 2 are for dimension

[David Hess]

Devices with multiple-emitter inputs (SN74 and SN74S series) are exceptions. Since no voltage greater than 5.5 V should be
applied to the inputs (because if exceeded, the base-emitter junction at the inputs breaks down), the inputs of these devices must
be connected to the supply voltage VCC via series resistor RS (see Figure 11). This resistor should be dimensioned such that
the current flowing into the gate or gates, which results from overvoltage, does not exceed 1 mA. But, because the high-level
input current of the circuits connected to the gate flows through this resistor, the resistor should be dimensioned so that the
voltage drop across it still allows the required high level. Equations 1 and 2 are for dimension

The warning also applies to many or all L (lower power) and H (high speed) TTL gates.

TI's description of the problem is wrong or at least massively incomplete.  Breakdown of the base-emitter junction is a secondary concern.  The primary problem is that the input transistor's reverse beta (reverse current gain) will allow current to flow backwards if the emitter is pulled above the base limited only by the reverse beta.  As shown below in a TTL NAND gate, the base is held at about 3 x Vbe maximum or 2.1 volts with a base current of about 725 microamps through the 4 kilohm resistor in series with the base.  If the reverse beta is 10, that will result in an input current of 7.25 milliamps with the input tied to Vcc and a dissipation of 26 milliwatts in the input transistor per input forced high.  And the reverse beta could be several times higher.  My personal experience is that the chips will run noticeably warmer and often fail after a short period of time.

Later TTL families including LS (low power schottky) used diode or PNP inputs so did not suffer from this issue and may have their inputs tied to Vcc safely.