Electronics > Projects, Designs, and Technical Stuff
Is it OK to directly tie logic inputs to Vdd?
artag:
In boards consisting of many common SSI and MSI parts, production test could be done by in-circuit testers which would exercise the parts using library tests. Tying an input high or low made those library tests unusable so they had to be modified -- at a cost of time and test coverage - to use only the available pins. Feedback (eg a latch configured as a counter such that an output pin change could affect an input) was also a problem.
I doubt that many tests are performed with that sort of equipment these days. Functional testers which test the circuit functionality as designed rather the components as specified are harder to program but may be faster. Self tests can give partial coverage. FPGAs and other programmable devices don't have library definitions. So these restrictions are less important than they once were, but design for manuacturing is still important and thought should be given to test and repair when the circuit is designed.
mzzj:
http://www.ti.com/lit/an/sdya009c/sdya009c.pdf
if a high level is required, it should be connected with a voltage source corresponding with a
high level. In general, this is the positive supply voltage VCC. Figure 10 shows how, in the previously mentioned cases, a fixed
potential should be connected to unused inputs. Note that a high level should be applied to the unused inputs of an AND
(NAND) function and a low level to unused inputs of an OR (NOR) function.
Devices with multiple-emitter inputs (SN74 and SN74S series) are exceptions. Since no voltage greater than 5.5 V should be
applied to the inputs (because if exceeded, the base-emitter junction at the inputs breaks down), the inputs of these devices must
be connected to the supply voltage VCC via series resistor RS (see Figure 11). This resistor should be dimensioned such that
the current flowing into the gate or gates, which results from overvoltage, does not exceed 1 mA. But, because the high-level
input current of the circuits connected to the gate flows through this resistor, the resistor should be dimensioned so that the
voltage drop across it still allows the required high level. Equations 1 and 2 are for dimension
David Hess:
--- Quote from: mzzj on December 03, 2019, 06:51:12 pm ---Devices with multiple-emitter inputs (SN74 and SN74S series) are exceptions. Since no voltage greater than 5.5 V should be
applied to the inputs (because if exceeded, the base-emitter junction at the inputs breaks down), the inputs of these devices must
be connected to the supply voltage VCC via series resistor RS (see Figure 11). This resistor should be dimensioned such that
the current flowing into the gate or gates, which results from overvoltage, does not exceed 1 mA. But, because the high-level
input current of the circuits connected to the gate flows through this resistor, the resistor should be dimensioned so that the
voltage drop across it still allows the required high level. Equations 1 and 2 are for dimension
--- End quote ---
The warning also applies to many or all L (lower power) and H (high speed) TTL gates.
TI's description of the problem is wrong or at least massively incomplete. Breakdown of the base-emitter junction is a secondary concern. The primary problem is that the input transistor's reverse beta (reverse current gain) will allow current to flow backwards if the emitter is pulled above the base limited only by the reverse beta. As shown below in a TTL NAND gate, the base is held at about 3 x Vbe maximum or 2.1 volts with a base current of about 725 microamps through the 4 kilohm resistor in series with the base. If the reverse beta is 10, that will result in an input current of 7.25 milliamps with the input tied to Vcc and a dissipation of 26 milliwatts in the input transistor per input forced high. And the reverse beta could be several times higher. My personal experience is that the chips will run noticeably warmer and often fail after a short period of time.
Later TTL families including LS (low power schottky) used diode or PNP inputs so did not suffer from this issue and may have their inputs tied to Vcc safely.
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