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| Is it OK to directly tie logic inputs to Vdd? |
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| 741:
Typically, generally that is, when a pin is meant to be always at logic 1. Just now, I have a long route to Vdd on a Veroboard PIC design. I could have gone directly "through" an un-used pin (these default to input). In the attached image, is it safe to wire pin RA7 to Vdd? Is it "better=safer" to always use say a 1k, 10k etc (even if the pin is meant to always be at logic 1)? |
| T3sl4co1l:
As long as the port initializes in Hi-Z, weak pull-up/down, or logic-high state, and is never changed to a state other than those, yes. Tim |
| MarkF:
In the good old days, tying a pin directly to Vdd would cause problems with TTL logic. I do not know how necessary it still is today. I always go through a resistor for a 'high' logic state. More out of habit I suppose. |
| Ian.M:
Its almost always safe to tie a CMOS *INPUT* direct to either supply rail. Its *NOT* safe to tie old bipolar true TTL inputs direct to Vcc as glitches on Vcc could cause latchup and destroy the chip. However tying MCU I/Os direct to a rail is strongly frowned upon. You may see it in cost-minimised high volume products, but all it takes is for the port output latch to be in the opposite state then for a glitch* or software bug to make the pin an output and there is a high risk of device damage or destruction. The minimal cost solution to unused I/Os is to set them as outputs and set them low. Veroboard implies a prototype so active software development with a high risk of bugs. If the PIC is socketed, crop that pin of the socket so you can use the track for power. If not, isolate its pad and use a jumper for the power rail, track side if you have to. * e.g. a bit-flip due to a cosmic ray cascade, even though such events are extremely rare at sea level, or due to a power transient. |
| SiliconWizard:
--- Quote from: Ian.M on December 03, 2019, 03:37:43 pm ---Its almost always safe to tie a CMOS *INPUT* direct to either supply rail. Its *NOT* safe to tie old bipolar true TTL inputs direct to Vcc as glitches on Vcc could cause latchup and destroy the chip. --- End quote --- Oh yeah, I remember that. --- Quote from: Ian.M on December 03, 2019, 03:37:43 pm ---However tying MCU I/Os direct to a rail is strongly frowned upon. You may see it in cost-minimised high volume products, but all it takes is for the port output latch to be in the opposite state then for a glitch* or software bug to make the pin an output and there is a high risk of device damage or destruction. The minimal cost solution to unused I/Os is to set them as outputs and set them low. --- End quote --- I agree with this. I personally don't do it, especially with software-configurable pins, way to dangerous. A way to kill your device due to a stupid bug, no thanks! There's also the slight possibility that said pin would get "zapped" for any reason during the lifetime of the product (eg: ESD), thus possibly shorting the power supply. Whether this is an acceptable failure mode is up to you, but it may not be. So yes: if we're talking about typical GPIOs - just set unused ones as outputs, and you're done. If there's a software bug and some of them would not be set as outputs, the only thing you'll get is an increased power consumption, not a kill of your device. On some MCUs, you can also disable the GPIO entirely - it gets powered off - instead. Now if some pin REALLY requires to be "tied" to Vdd, I'll use a series resistor to limit any potential damage, but as said above, the cases where it's really *required* are usually a few, so that adds almost no cost or PCB area. |
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