Electronics > Projects, Designs, and Technical Stuff
Is it safe to connect inputs to VCC directly
wraper:
TomS_:
I asked about this some time ago and got some reasonably good answers:
https://www.eevblog.com/forum/projects/pull-up-resistors-technically-necessary-vs-preference/msg1699586/
Short answer: I dont bother with pull up/down resistors any more except when I might need to override a signal.
tggzzz:
--- Quote from: ataradov on February 04, 2020, 09:00:40 pm ---
--- Quote from: TimFox on February 04, 2020, 08:56:45 pm ---Connecting inactive inputs to ground or Vcc through appropriate resistors allows testing the IC in-circuit by driving the input from a “stiff” test voltage on a test jig. This is part of design-for-test process.
--- End quote ---
This argument is just strange. Why would you ever want to override an input, which value is fixed at the design stage? What are you testing here exactly?
--- End quote ---
Not testing the design; that was done earlier.
Testing that this instance of the design has been manufactured correctly, e.g. components inserted correctly, no short circuits etc. That requires a completely different set of tests.
tkamiya:
The idea is, you don't want input of a CMOS gate floating around. You can tie it to ground, VCC, via or without registers. Just make sure the voltage you tie to is equal to or less than power to the chip. I usually tie to VCC or ground, whichever is closer.
David Hess:
If multiple Vcc supplies are used then that would be a good reason to use series input resistors to limit the current but in the common case, I do not know of any reason the input cannot be directly connected to either power rail.
Early TTL is a special case because of its common base multiple emitter input structure which required series resistors if an input was pulled up to Vcc.
--- Quote from: wraper on February 04, 2020, 09:35:29 pm ---
--- Quote from: EEEnthusiast on February 04, 2020, 04:08:58 am ---Direct shorting of inputs to Vcc or Ground can lead to latchup in some CMOS families. It is always safe to use some pull-up to limit this current.
--- End quote ---
How resistor is supposed to limit current through MOSFET gates when latch-up does not even cause current flowing through them?
--- End quote ---
It does not have anything to do with the gate; it is insulating after all. Latchup occurs when carriers are injected into the substrate and they activate the parasitic SCR structure present in a junction isolated CMOS process. This can happen if the input or output ESD protection diodes are forward biased with enough current.
I have personally witnessed it a few times when static jumped between a finger and a CMOS logic board and one CMOS IC became an SCR crowbar across the power supply.
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