Electronics > Projects, Designs, and Technical Stuff
Is it safe to connect inputs to VCC directly
wraper:
--- Quote from: MasterT on February 05, 2020, 01:21:26 am ---
--- Quote from: wraper on February 05, 2020, 12:38:50 am ---
--- Quote from: MasterT on February 05, 2020, 12:30:02 am ---Inputs are not designed to pass much current, so there is "probability" latching-up, and it's easier to install a resistor than estimate 12-20 inputs/outputs interference to each other .
--- End quote ---
Again, please explain how MOSFET gates tied to Vdd/Vss are supposed to pass any current. Latch-up does not result in current passing through the gates.
--- End quote ---
I 'd refer to TI - White Paper
SCAA124 – April 2015
Latch-Up
Marty Johnson, Roger Cline, Scott Ward, Joe Schichl
--- Quote ---During the design of signal ESD protection structures, there can be
intentional SCRs employed that encourage selected parasitic PNPN diodes to trigger under an ESD event.
While ESD is an unpowered event, this is not a concern and actually desirable. However, during normal
operation since an intentional SCR could exist between a signal pin to ground and the signal pin could be
tied or driven to a “hi” state, care must be taken by using design rules on the product to limit effects of
Signal Latch-Up, thereby, mitigating the effect of excursion that could trigger the signal ESD SCR and
effectively short the signal to ground. If a signal pin is tied or driven to a “lo” state, then the signal voltage
is below the ESD SCR holding voltage and signal Latch-Up will not occur.
--- End quote ---
In short, there is certain "design rules".
--- End quote ---
You forgot to mention that in only happens when there is intentionally made SCR structure on inputs for ESD protection.
MasterT:
--- Quote from: wraper on February 05, 2020, 01:13:55 am ---
--- Quote ---Cellular towers and mobile phones all around us, no need to be in aerospace.
--- End quote ---
And in that case you better tie things hard with low impedance paths instead of using resistors which cannot quench RF interference.
--- End quote ---
I'd not be so sure about 5 GHz, that connecting pin - essentially small piece of antenna, to ground is more safe. Another end may have 1/4 length to be hardly energized.
I can't comment what kind of SCR is in use nowadays, last time I seen CMOS in X-ray in 90-th. But my understanding, since human body doesn't change much since than, has same charge capacity and lethal for CMOS energy, the same time size of components (MOSFET, shottky diodes ) shrink substantially, means that simple diode-R-diode chain may not be enough to satisfy same ESD standard. So, manufacturers have to incorporate much more sophisticate protection, SCR or whatever.
james_s:
--- Quote from: wraper on February 05, 2020, 12:13:40 am ---More like stupid practice how to increase manufacturing costs and problems due to higher component count. Also you reduce noise immunity or robustness against board contamination or tin whiskers. Say CMOS output (connected to input) has much lower impedance than a few k resistor you would use as pull-up.
--- End quote ---
How does tying unused inputs to Vcc or ground increase manufacturing cost and increase component count?
Miti:
--- Quote from: ataradov on February 04, 2020, 09:00:40 pm ---
--- Quote from: TimFox on February 04, 2020, 08:56:45 pm ---Connecting inactive inputs to ground or Vcc through appropriate resistors allows testing the IC in-circuit by driving the input from a “stiff” test voltage on a test jig. This is part of design-for-test process.
--- End quote ---
This argument is just strange. Why would you ever want to override an input, which value is fixed at the design stage? What are you testing here exactly?
Why don't you decouple the inputs that are driven by other outputs? So you could override those as well for testing?
What is so special about pins that must have fixed value?
--- End quote ---
To kill a clock so the MCU doesn't start running the code. To keep an MCU in reset or otherwise it would interfere with your ICT or boundary scan. To pull up a "test enable" pin to put a JTAG compatible device in... well... test mode.
This is a strong requirement in our DFT guidelines.
ataradov:
--- Quote from: Miti on February 05, 2020, 02:33:21 am ---To kill a clock so the MCU doesn't start running the code. To keep an MCU in reset or otherwise it would interfere with your ICT or boundary scan. To pull up a "test enable" pin to put a JTAG compatible device in... well... test mode.
--- End quote ---
Those are provisions for dedicated pins. I'm not arguing with that.
I'm asking specifically about single 74-series gates. Let's say I use 4-NAND and I only need 3 inputs. All I need is to force one other input to be always high. Any testing like that should happen through other 3 pins. This extra pin carries no function in the design. Unless you assign it a function to be a test input.
Navigation
[0] Message Index
[#] Next page
[*] Previous page
Go to full version