Electronics > Projects, Designs, and Technical Stuff
Is it safe to connect inputs to VCC directly
tggzzz:
--- Quote from: ataradov on February 05, 2020, 02:37:45 am ---
--- Quote from: Miti on February 05, 2020, 02:33:21 am ---To kill a clock so the MCU doesn't start running the code. To keep an MCU in reset or otherwise it would interfere with your ICT or boundary scan. To pull up a "test enable" pin to put a JTAG compatible device in... well... test mode.
--- End quote ---
Those are provisions for dedicated pins. I'm not arguing with that.
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And that's an example of the problems caused by omitting context. You did write. (with my emphasis)...
--- Quote from: ataradov on February 04, 2020, 09:00:40 pm ---
--- Quote from: TimFox on February 04, 2020, 08:56:45 pm ---Connecting inactive inputs to ground or Vcc through appropriate resistors allows testing the IC in-circuit by driving the input from a “stiff” test voltage on a test jig. This is part of design-for-test process.
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This argument is just strange. Why would you ever want to override an input, which value is fixed at the design stage? What are you testing here exactly?
...
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ataradov:
--- Quote from: tggzzz on February 05, 2020, 08:23:56 am ---Well, you did write...
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There is a difference between the pin that must normally be held high when not in use, like programming and test pins, and a pin that is absolutely never needs to be overridden, like that 4th unused input on a 4-NAND gate.
Nobody tries to override random parts of the circuit "for testing". That's just nonsense.
tggzzz:
--- Quote from: ataradov on February 05, 2020, 06:56:57 am ---
--- Quote from: aix on February 05, 2020, 06:25:54 am ---I do realise that your question is broader than this. However, this particular example got me wondering: to get 3-NAND from 4-NAND, what are the pros and cons of tying one input high vs tying two of the four inputs together.
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I have no idea. I don't think there is a significant difference. Intuition tells me that having one input fixed is better, it avoids one more thing changing, but I don't know for sure.
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In some cases the extra load capacitance might be an issue.
David Hess:
--- Quote from: aix on February 05, 2020, 06:25:54 am ---
--- Quote from: ataradov on February 05, 2020, 02:37:45 am ---Let's say I use 4-NAND and I only need 3 inputs.
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I do realise that your question is broader than this. However, this particular example got me wondering: to get 3-NAND from 4-NAND, what are the pros and cons of tying one input high vs tying two of the four inputs together.
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Except for edge cases where doubling the capacitance and leakage matter, you can always do that and it is even the recommended method for TTL where it does not even increase the fan-in of a single gate.
iMo:
As indicated by above posters - connecting a CMOS input "directly to Vcc or Gnd" of the SAME chip is safe.
What could be an issue - and that is what the people try to indicate above - is when somebody "thinks the CMOS input is connected directly to the Vcc or Gnd" (mind the word "directly"), but in reality:
a) the wire is rather long - it pickups transients from its surrounding
b) the Vcc or Gnd potential (at the point of connection) is DC biased (ie a voltage drop on Vcc or Gnd rails) against the Vcc or Gnd at the CMOS chip
c) the Vcc voltage at the CMOS chip vs. the voltage at the point of connection differ during powerup
d) the Vcc voltage at the CMOS chip vs. the voltage at the point of connection is noisy..
etc.
In those cases there could be a peak current flowing through the first two (upper or lower) clamping diodes (the input of a CMOS logic gate consists typically of 2 diodes - 1 resistor - 2 diodes) and the excessive current may cause some issues in the silicon of that CMOS chip. As I wrote above in past the "connection points" where the unused inputs were connected to were sometimes "far away" of the actual CMOS chip, and/or were connected to different Vcc and Gnd power rails. Thus adding a resistor close to the CMOS input pin helped to limit those spurious current peaks.
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