ADevices datasheet mess, AD7764 pin MCLK voltage levels

[Yansi]

Hi!

just working on a design with an AD7764 ( datasheet). Starting to realize, I really should have picked a different specimen, as this one is rather pissing me off with the way the datasheet is put.

It all begun with finding that the digital domain supports 2.5V only - well, that is not that big issue, rather very inconvenient.
Then I realized the complicated power supply scheme and all that nonsense. Just look at figure 53, which is one unreadable mess.

Then the real fun begins. What kind of voltage level do I need for the MCLK pin?  Is it a digital IO, i.e. needs maximum of 2.5V?  Why there is all over the datasheet tables mentioned "MCLK Amplitude 5V"?  Just wtf? Even Table 2 at page 6 top lists MCLK range as 2.25 to 5.25V, amplitude.  What does amplitude mean in this context?

I know I should be asking this the Analog Devices support, but these guys are a bunch of ignorants, that do not bother responding. Las time I reported a rather critical error in the AD9951 datasheet, and guess what, the error is still there, they haven't bothered to respond.

Rant end, thank you for making guesses about the MCLK pin.
Y

[dmills]

Page 6 of the datasheet, quite straightforward 2.25 to 5.25V, Vih = 0.8Vdd, Vil = 0.2Vdd, so either a 2.5V cmos a 3.3V cmos or a 5V cmos clock should be fine.

Generally with delta sigma converters, more clock amplitude is better then less because it tends to reduce the aperture jitter.

Figure 53 could be clearer, but basically the caps go on the back of the board and a local star ground is desired, this is very much par for the course with high precision converters.

Regards, Dan.

[Yansi]

I disagree. How can you apply 5V signal to a pin, that is, seemingly, only a 2.5V digital input, with 2.8V absolute maximum input voltage and call it straightforward? Or is this any kind of non-written practice, to overdrive ADC clock inputs beyond the VDD/GND into the substrate diode conduction, presuming the clock source has enough impedance not to burn the shit out of the input?
In that case this should be explicitly stated in the datasheet, so that people not usually working with such ADCs do not get confused by nasty design practices.

I understand the starpoint concept, but the drawing is useless, it is a heap of spaghetti, not to mention that putting a double sided component load won't happen in many cases, unless the rest of board is very complex too so it is wise to pay for the technology to produce such boards.

[ovnr]

MCLK: Fairly certain that the 2.25-5.25V spec is wrong. Just feed it with the same voltage as all the other digital inputs: 2.5V.

And welcome to the real world, where datasheets are wrong sometimes. It's absolutely delightful; I fondly remember a microchip datasheet with the wrong damn pinout, and the correct one tucked away in the errata sheet. I mean, really?

[Yansi]

Hello!  Finally got time to spend on this little bastard. Now having big troubles understanding the behavior of the serial interface.

After throwing another half a day on the bastard, trying to solve issue where I could not supposedly read data from it correctly, I finally concluded, after manually decoding frames on an oscilloscope, that the device really sends out junk and there is none issue with my reception of data.

Lets look what happens right after reset: Just after releasing RESET signal of the AD7764, it spits out 0x089CD6D8. But I call bullshit on that, let me explain why:

The ADC spits 32bit frames, marked by /FSO=low.  According to Figure 2 in the device datasheet, this frame contains 24bits of conversion result and 8 bits of status.  Table 12 describes meaning of those bits.
So I have received 0xD8 as a status.   The lowest three bits shall be zero - yes they are. However!  I got reported bits 4 and 3 to be 11, meaning I have 128x decimation rate. But I don't! I have 256x selected. (Verified both by voltage at pin DEC_SEL and the frequency of /FSO signal). Also, bits 7 and 6 are high, meaning I get FILTER_SETTLE (I can't! I have just reset the device!) and OVRange. I don't. There is about 50uV on the input pins.

And by the way, when the device is held reset/powered down, the OVR pin reports over-range continuously.  Wtf? Kind of unexpexted functionality.

I think there is something broken with this device, but it does seem that it is not only the documentation, but the part itself too.

I just don't know what to test next. Other than scrapping the whole design and picking different ADC next time.

Any ideas, what might be wrong?

Thanks
Y

[amyk]

MCLK: Fairly certain that the 2.25-5.25V spec is wrong. Just feed it with the same voltage as all the other digital inputs: 2.5V.

I don't think so. The official evaluation board for it contains a 5V 40MHz crystal oscillator.

Requiring special signal levels for clock inputs is not unusual; the Intel 8080 is a notable example.

[Yansi]

Why would you feed 5V clock if the rest of the digital is 2.5V maximum?

Nowhere in the datasheet there is specified, that MCLK pin can accept voltages above 2.5V.  And it seems it accepts 2.5V MCLK very  correctly. I get all other clock outputs to clock at the correct speeds. (SCO at 16MHz and /FSO at 62.5kHz).
So I think that 5V AMPLITUDE as they write is indeed very incorrect, as 5V amplitude would in fact be 10Vpp.


And to the story update above: The device sends total garbage after reset.  First strange thing is it starts with /FSO already asserted (low), then spits out a frame, that clearly can be even way longer than 32 bits.
But garbage not only after reset. Even if I skip several (hundreds) of frames and then sync the SPI slave to it, it still reads gibberish.

I need to get to a proper logic analyzer to see what is going on there. My scope with just 2 channels is very limiting in debugging this bastard.


This in the attachment is what I get after releasing reset.  With /FSO already low, clocks (SCO) start running, and then SDO spits out this at least 42 bits long frame of bullshit. And yes, I have checked many times, taht /FSI is high and that SDI is low. I even do not trust my measurements after this...

[Siwastaja]

Why would you feed 5V clock if the rest of the digital is 2.5V maximum?

Because the clock is not just a clock to a simple digital interface logic; this clock is part of the ADC conversion itself, which, by definition, is a more "analog" thing, than digital.

Avdd domains seem to be something you can power up from 5V. It's possible that the MCLK is a direct input of the 5V Avdd domain!

The datasheet seems clear about the MCLK input amplitude: 2.25V to 5.25V, as you have noticed yourself. Do you have a compelling reason to think that this is an error? Why do you think there are substrate diodes to the digital 2.5V supply domain? You can easily verify this by a simple measurement.

Amplitude is a stupid choice of words, because it can mean anything ( https://en.wikipedia.org/wiki/Amplitude ), but really, is there ambiguity in this particular case, with a nice single-ended unipolar square wave? It must mean peak-to-peak.

[Siwastaja]

Now I see where your confusion comes from. In absolute maximum ratings, they specify:
Digital Input Voltage to Ground   to +2.8V

They never specify anything else for MCLK in abs.max ratings, and then they call MCLK a "digital input" in Table 2.

Therefore, absolute maximum rating for MCLK is 2.8V according to the datasheet. Elsewhere, they suggest you can apply "amplitude" of 5.25V, which is confusing, and now the reader starts wondering about their definition of "amplitude" to solve the mystery. Which doesn't help, because no matter the definition, the contradiction stays; alternative definitions of amplitude would just mean even higher voltage (such as 10Vp-p).

So typical datasheet.

Most likely, the real range is 5V, and you are just "formally" running the device outside the absolute maximum ratings due to documentation error, but still run the device as intended by the actual designer. Happens all the time. But do document this error clearly as a schematic note, in code as a comment, etc., to help future generations.

[Yansi]

I am glad that you finally found the same: MCLK is NOT specified for 5V anywhere else, than in the "amplitude notice".
I better follow the absolute maximum ratings, than to trust  any such comment in the datasheet.
There have not to be a substrate diode (there isn't one, I have measured), but still a missing substrate diode does not mean more voltage can be applied.  (It seems there may be a substrate diode from MCLK to AVDD). So did I chose to supply 2.5V digital clock, to be safe.

And this is not the only mistake in the datasheet, it is absolutely full of such BS:
 - Try finding the bits ST4:0 from Figure 2. Hint: You won't find them. They are D7:D3 in Table 12.
 - Figure 53: Some unreadable spaghetti ghetto.
 - Figure 54: The ADR444 reference. If you really wire it this way, it will oscillate like hell. (Sure idiot me wired it the recommended way!)
 - Then there was the issue with wrong Table 18 (fortunately, they at least fixed this).
 - I would probably remember more I have found.

I would gladly pass this knowledge to future generations, if I could get that damn thing to do what it is supposed to. 

I would be also very glad, if someone would come and said: Hey, you did this bullshit, hence it is not working properly. But I just can't find what I have done wrong. The MCU (SPI slave) connected to the ADC seems to be reading correctly what's present on the wires. I can decode the same gibberish using my DSO, as noted above.

So we have other interesting issues to look at:
 - Minor: Why OVERRANGE pin is indicating over-range, when device in powerdown (held reset).
 - Major: Why device is starting with /FSO already low, when released from reset?
 - Major: How on earth is it possible, it can send way longer frames just after reset?
 - Major: Received data make no sense.

Here's how it's wired up. If anyone see any error, scream loudly please!

The reference is from ADR444. Clean stable 4.096V.  DECRATE is grounded (using a  74LVC125 gate, but I wouldn't suspect that).  SDI is held low all the time, /FSI is held high all the time.  After releasing reset, SCO produces 16MHz (MCLK is 32MHz), /FSO produces 62.5kHz.