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| Is there any variable DC-DC converter suitable for pre-regulation? |
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| T3sl4co1l:
Yeah, you completely made an oscillator, U3 has no feedback or compensation and the transistor is wide open. It might simulate stable under some circumstances but it will definitely oscillate in practice. Tim |
| bloguetronica:
Hi Tim, Did some transients and steady state simulations, and indeed that oscillation happens. So, I've decided to stop using an op-amp as a comparator and decided to use the LMV331 comparator instead. The datasheet doesn't mention an hysteresis figure, and also suggests that can the comparator can be used where no hysteresis is desirable (with the due PCB layout cautions). So, I've decided to redraw the circuit. But the transient and steady state simulations seem to show convergence errors. The DC sweep works as expected. The new circuit shows a much more precise current limiting (indicative of problems with the old circuit). It seems I'll have to build the circuit using the comparator to see how well it works. The pre-regulator will be figured out later, but I'll use the bipolar transistor solution presented before here, somewhere. The CC LED indicator will not be used, because it is not possible to use in this solution without messing up the circuit. See "Sim2.png" for the new circuit. A comparator should be stable. I didn't used before because I was worried about the hysteresis that these guys normally show. However, since I have some degree of negative feedback, the voltage at the inputs will have a tendency to be equal in the CC condition (as also simulated with the OPA703 op-amp). That means the comparator will work in its "active" region (perhaps "unstable" by other means). Thanks, and lets see how this goes. Kind regards, Samuel Lourenço |
| T3sl4co1l:
Nooooo no no no! A comparator just oscillates more! Are you trying to make a fault latch instead? Then you need a latch. You can't have a comparator turn off the signal that turns it on, that's the definition of a (relaxation) oscillator. But a stable, linear current limit, just control the loop gain and phase so it's stable. Which means, limiting the gain of that transistor (typically, a base voltage divider and an emitter degeneration resistor are added), and compensating the amp (an R+C from OUT to -IN, and a series resistance to -IN from whatever source is feeding it, if necessary). Edit: also, have you checked the LMV331 datasheet? It's a 5V part, and propagation delay is probably as high as the rest of the circuit. Sanity check! I don't know what model is inside that part there, but I suspect if you test it alone you will find it bears no resemblance at all to a real LMV331! Tim |
| bloguetronica:
Hi Tim, No, a fault latch is very undesirable. I just want to implement current limiting, and that is why I opted for an op-amp in the first place, because I want the circuit to operate in the linear region (no hysteresis whatsoever, in any shape or form). I was expecting that this comparator could be used like so, since it is stable in open loop and supposedly has no hysteresis. If it has, if even by a tiny ammount, then the whole circuit would act indeed as a relaxation oscillator. So, how do I limit the gain of the transistor? How do I stabilize the unstable op-amp? R+C in parallel from the output to the input? Or in series? A rough schematic of this sub-circuit will do. Then I would tweak the values. I can't find examples on how to use an op-amp as a comparator of sorts. As for the 5V supply, it is implemented in the simulation and will be implemented in real life, from a completely independent regulator that is fed by the 24V rail. No worries! Kind regards, Samuel Lourenço |
| T3sl4co1l:
Your problem is thinking it's a comparator at all -- a comparator is a one-bit analog-to-digital converter. An ideal comparator has no linear range whatsoever. We could maybe use one in a PWM circuit, but there's nothing linear and stable about one! A fault latch isn't uncommon in power control functions -- if not in bench supplies -- and that would be an expected use for a comparator. A latch is a digital logic element, so a comparator would trigger it -- hence why I asked to make sure. :) Rather, what you're looking for is more of a "fuzzy logic" condition: you want the current error amp to be inactive (saturated output-low) when the output current is in the range 0...IREF, and active above there. What's more, you require active operation to be limited in speed, so it isn't chasing its tail (oscillating) in the active range. Yes, R+C in parallel with the amp, you may remember this: https://www.seventransistorlabs.com/Images/Limiter2.png The op-amp is the current error amp, and the R+C across it is the compensation. R5 is the series input resistor. In this case, you can ignore everything else in the circuit (but using this circuit instead of the two error amps is far superior!). Tim |
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