It's a phenomenon known to programmers as a "Heisenbug", after the Heisenberg quantum uncertainty principle, which states that it is impossible to measure/observe a system without affecting its behavior.
Attach a scope probe permanently to the circuit and forget about it

Seriously, I suspect that probe capacitance provides some noise reduction which eleminates earlier problems with TDI that you didn't even notice. If the probe is removed, this problem causes the JTAG probe to identify the chip incorrectly and send different commands.
independent of clock rate
It's probably capacitive crosstalk between CLK and TDI. The JTAG sends a clock edge which causes a spike on TDI and then immediately reads TDI state, regardless of clock rate, before the spike has enough time to dissipate. Or perhaps the DUT samples TDO immediately after a clock edge, interprets a command wrong, sends wrong response, the JTAG outputs a wrong next command.