Electronics > Projects, Designs, and Technical Stuff

JTAG only works when scope is attached

(1/3) > >>

twam:
Hi everybody,

I've got a strange problem (at least for me  ;D) and no idea what could be the issue. I'm trying to talk to an ECP5 FPGA via JTAG using an FT232H. Between the FT232H GND, TDO, TDI, TMS and TCK are connected. The problem is, that I only read out the correct chip ID if I listen on the TCK channel with the scope and a passive (!) probe. The problem is independent of frequency (10 kHZ to 25 MHz).

In the working case the signals look like this (TCLK_A = Active probe on TCK, TCLK_P = Passive prob on TCK):



And when I disconnect the passive probe on TCK it looks like this (different signal on TDO)



Any hints want could be causing this issue?

cowana:
I suspect that without the scope connected, you're seeing ringing on the TCK line, causing the FPGA to incorrectly register two bits.

With a small amount of capacitance connected (the passive scope probe), the rise time is slugged, stopping the ringing and making the FPGA correctly see a single edge.

Can you try connecting a small resistor in the TCK line between the FT232H (22R?) to slow the rise time? Alternatively adding a capacitor to the board (10pf) should have the same effect as the scope probe.

Note that edge rise-times are separate to frequency - it's not surprising you see the same issue at 10kHz or 25MHz.

rs20:
Strange issue. Assuming it's not caused by something you're not mentioning, and assuming that attaching the group clip of the oscilloscope alone doesn't have any effect, all I can think is to suggest that maybe there's an interfering noise source, and the capacitance of the probe is shunting some of the noise away. Make sure you're using 1:10 mode on your probe, and if that still causes it, try replacing the probe connection with a 10-100pF cap to ground, as a way to validate my hypothesis.

magic:
It's a phenomenon known to programmers as a "Heisenbug", after the Heisenberg quantum uncertainty principle, which states that it is impossible to measure/observe a system without affecting its behavior.

Attach a scope probe permanently to the circuit and forget about it ;D

Seriously, I suspect that probe capacitance provides some noise reduction which eleminates earlier problems with TDI that you didn't even notice. If the probe is removed, this problem causes the JTAG probe to identify the chip incorrectly and send different commands.


--- Quote ---independent of clock rate
--- End quote ---
It's probably capacitive crosstalk between CLK and TDI. The JTAG sends a clock edge which causes a spike on TDI and then immediately reads TDI state, regardless of clock rate, before the spike has enough time to dissipate. Or perhaps the DUT samples TDO immediately after a clock edge, interprets a command wrong, sends wrong response, the JTAG outputs a wrong next command.

tggzzz:
Insufficient information to be able to diagnose a signal integrity problem.

Specify the probes used.
Show the schematic, and preferably the PCB layout.
Show a photo of your probing technique.

That's all necessary when dealing with analogue signals - and your signals are analogue.

Navigation

[0] Message Index

[#] Next page

There was an error while thanking
Thanking...
Go to full version
Powered by SMFPacks Advanced Attachments Uploader Mod